DATASHEET
ZL1505
Synchronous Step-Down MOSFET Drivers
The ZL1505 is an integrated high-speed, high-current
N-channel MOSFET driver for synchronous step-down DC/DC
conversion applications. When used with Zilker Labs Digital-
DC™ PWM controllers, the ZL1505 enables dynamically
adaptive dead-time control that optimizes efficiency under all
operating conditions. A dual input PWM configuration enables
this efficiency optimization while minimizing complexity within
the driver.
Operating from a 4.5V to 7.5V input, the ZL1505 combines a
5A, 0.5W low-side driver and a 3A, 0.8W high-side driver to
support high step-down buck applications. A unique adjustable
gate drive current scheme allows the user to adjust the drive
current on both drivers to optimize performance for a wide
rage of input/output voltages, load currents, power MOSFETs
and switching frequencies up to 1.4MHz. An integrated 30V
bootstrap Schottky diode is used to charge the external
bootstrap capacitor. An internal watchdog circuit prevents
excessive shoot-through currents and protects the external
MOSFET switches.
The ZL1505 is specified over a wide -40°C to +125°C junction
temperature range and is available in an exposed pad DFN-10
package.
FN6845
Rev 3.00
February 25, 2011
Features
• High-speed, high-current drivers for synchronous N-channel
MOSFETs
• Adaptive dead-time control optimizes efficiency when used
with Digital-DC controllers
• Integrated 30V bootstrap Schottky diode
• Capable of driving 40A per phase
• Supports switching frequency up to 1.4MHz
- >4A source, >5A sink low-side driver
- >3A source/sink high-side driver
- <10ns rise/fall times, low propagation delay
• Adjustable gate drive strength optimizes efficiency for
different V
IN
, V
OUT
, I
OUT
, F
SW
and MOSFET combinations
• Internal non-overlap watchdog prevents shoot-through
currents
Applications*
(see page 12)
• High efficiency, high-current DC/DC buck converters with
digital control and PMBus™
• Multi-phase digital DC/DC converters with phase
adding/dropping
• Power train modules
• Synchronous rectification for secondary side isolated power
converters
Related Literature*
(see page 12)
•
ZL2004
Adaptive Digital DC/DC Controller with Current
Sharing
HSEL
VDD
PWMH
LEVEL
SHIFT
SHOOT-
THROUGH
PROTECTION
BST
GH
VDD
SW
GL
PWML
ZL1505
GND
LSEL
FIGURE 1. ZL1505 BLOCK DIAGRAM
FN6845 Rev 3.00
February 25, 2011
Page 1 of 13
ZL1505
Typical Application Circuit
The following application circuit represents the typical implementation of the ZL1505 (Notes 1, 2).
V
IN
4.5-14V
V
BIAS
4.5-7.5V
VIN
VDD
VIN
VMON
VDD
Power Train
Module
LSEL
HSEL
BST
GH
SW
GL
PWMH
ZL2004
PWML
XTEMP
SGND
VSEN+
ISENA
ISENB
VSEN-
PWMH
PWML
TEMP+
PWMH
VOUT
ZL1505
GND
PWML
GND
GND
CS+
CS-
TEMP-
FIGURE 2. POWER TRAIN MODULE USING ZL2004 PWM CONTROLLER
NOTES:
1. For V
DD
of 4.5V to 7.5V, the maximum V
IN
of the ZL1505 is 22.5V to 25.5V. ZL1505 input supply voltage range (V
IN
) is specified in Figure 2.
2. V
IN
for this application circuit is limited by the ZL2004 V
IN
of 4.5V to 14V.
FN6845 Rev 3.00
February 25, 2011
Page 2 of 13
ZL1505
Pin Configuration
ZL1505
(10 LD DFN)
TOP VIEW
HSEL 1
GH 2
SW 3
PWMH 4
PWML 5
*CONNECT TO GND
EPAD*
10 BST
9 VDD
8 GL
7 GND
6 LSEL
Pin Descriptions
PIN NUMBER
1
2
3
4
5
6
7
8
9
10
EPAD
PIN NAME
HSEL
GH
SW
PWMH
PWML
LSEL
GND
GL
VDD
BST
GND
TYPE (Note 3)
I
O
I/O
I
I
I
PWR
O
PWR
PWR
PWR
DESCRIPTION
High-side gate drive current selector. Connect to BST for maximum gate drive current;
connect to SW for 50% of maximum gate drive current.
Output of high-side gate driver. Connect to the gate of high-side FET.
Phase node. Return path for high-side driver. Connect to source of high-side FET and drain
of low-side FET.
High-side PWM control input.
Low-side PWM control input.
Low-side gate drive current selector. Connect to VDD for maximum gate drive current;
connect to GND for 50% of maximum gate drive current.
Ground. All signals return to this pin.
Output of low-side gate driver. Connect to the gate of low-side FET.
Gate drive bias supply. Connect a high-quality bypass capacitor from this pin to GND.
Bootstrap supply. Connect external capacitor to SW node.
Ground.
NOTE:
3. I = Input, O = Output, PWR = Power OR Ground.
Ordering Information
PART NUMBER
(Notes 4, 7)
ZL1505ALNNT (Note 5)
ZL1505ALNNT1 (Note 5)
ZL1505ALNNT6 (Note 5)
ZL1505ALNFT (Note 6)
ZL1505ALNFT1 (Note 6)
ZL1505ALNFT6 (Note 6)
NOTES:
4. Please refer to Tech Brief
TB347
for details on reel specifications.
5. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu
plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
6. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-
free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
7. For Moisture Sensitivity Level (MSL), please see device information page for
ZL1505.
For more information on MSL please see Tech Brief
TB363.
PART
MARKING
1505
1505
1505
1505
1505
1505
TEMP RANGE
(°C)
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
PACKAGE
Tape and Reel
(Pb-free)
10 Ld 3x3 DFN
10 Ld 3x3 DFN
10 Ld 3x3 DFN
10 Ld 3x3 DFN
10 Ld 3x3 DFN
10 Ld 3x3 DFN
PKG.
DWG. #
L10.3x3D
L10.3x3D
L10.3x3D
L10.3x3D
L10.3x3D
L10.3x3D
FN6845 Rev 3.00
February 25, 2011
Page 3 of 13
ZL1505
Absolute Maximum Ratings
Voltage Measured with Respect to GND
DC Supply Voltage for VDD Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 8V
High-Side Supply Voltage for BST Pin. . . . . . . . . . . . . . . . . . . . . -0.3V to 30V
High-Side Drive Voltage for
GH Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (V
SW
- 0.3V) to (V
BST
+ 0.3V)
Low-Side Drive Voltage for
GL Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (GND - 0.3V) to (V
DD
+ 0.3V)
Boost to Switch Differential (V
BST
- V
SW
) for
BST, SW Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 8V
Switch Voltage for SW Pin
Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (GND - 0.3V) to 30V
<100ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (GND - 5V) to 30V
Logic I/O Voltage for PWMH, PWML, LSEL Pins . . . . . . . . . . . . . -0.3V to 6V
HSEL Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . (V
SW
- 0.3V) to (V
BST
+ 0.3V)
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kV
GL Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500V
Latch Up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tested to JESD78
Thermal Information
Thermal Resistance (Typical)
JA
(°C/W)
JC
(°C/W)
10 Ld DFN (Notes 8, 9) . . . . . . . . . . . . . . . .
50
7
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-55°C to +150°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-55°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Gate Drive Bias Supply Voltage Range
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 7.5V
Input Supply Voltage Range, V
IN
. . . . . . . . . . . . . . . . . . . . . 3V to 30V - V
DD
Operating Junction Temperature Range, T
J
. . . . . . . . . . . . .-40°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
8.
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief
TB379.
9. For
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
PARAMETER
V
DD
= 6.5V, T
J
= -40°C to +125°C unless otherwise noted. Typical values are at T
A
= +25°C. Boldface limits
apply over the operating temperature range, -40°C to +125°C.
CONDITIONS
MIN
(Note 10)
TYP
MAX
(Note 10)
UNIT
BIAS CURRENT CHARACTERISTICS
I
DD
supply current
Not switching
–
110
180
µA
PWM INPUT CHARACTERISTICS
PWM Input Bias Current
V
PWM
= 5 V
V
PWM
= 0 V
PWM Input Logic Low, V
IL
PWMH or PWML
V
DD
= 6.5V
V
DD
= 5.0V
PWM Input Logic High, V
IH
PWMH or PWML
V
DD
= 6.5V
V
DD
= 5.0V
Hysteresis
PWMH or PWML
V
DD
= 6.5V
V
DD
= 5.0V
Minimum PWMH On-time to Produce GH Pulse, C
GH
= 0
t
PWMH,ON
(Note 11)
Minimum GH On-time Pulse, t
GH,ON
(Note 12)
C
GH
= 0
C
GH
= 3 nF, V
HSEL
= V
BST
Minimum PWMH Off-time to Produce Valid GH
Pulse, t
PWMH,OFF
C
GH
= 0
–
–
–
–
3.4
2.7
-
-
–
5
–
–
–
–
–
1.1
0.8
12
–
1
1.7
1.4
–
–
-
-
-
µA
µA
V
V
V
V
V
V
ns
–
-
–
14
20
17
-
-
-
ns
ns
ns
BOOTSTRAP DIODE CHARACTERISTICS
Forward Voltage (V
F
)
Forward bias current 100 mA
–
0.8
–
V
FN6845 Rev 3.00
February 25, 2011
Page 4 of 13
ZL1505
Electrical Specifications
PARAMETER
V
DD
= 6.5V, T
J
= -40°C to +125°C unless otherwise noted. Typical values are at T
A
= +25°C. Boldface limits
apply over the operating temperature range, -40°C to +125°C.
(Continued)
CONDITIONS
MIN
(Note 10)
TYP
MAX
(Note 10)
UNIT
THERMAL PROTECTION
Thermal Trip Point
Thermal Reset Point
–
–
150
134
–
–
C
C
UPPER GATE DRIVER CHARACTERISTICS
Driver Voltage (V
BST
– V
SW
)
High-side Driver Peak Gate Drive Current (Pull-up) (V
GH
– V
SW
) = 2.5V
HSEL connected to
BST
HSEL connected to
SW
High-side Driver Peak Gate Drive Current
(Pull-down)
(V
GH
– V
SW
) = 2.5V
HSEL connected to
BST
HSEL connected to
SW
High-side Driver Pull-up Resistance
(V
BST
– V
GH
) = 50mV
HSEL connected to
BST
HSEL connected to
SW
High-side Driver Pull-down Resistance
(V
GH
– V
SW
) = 50mV
HSEL connected to
BST
HSEL connected to
SW
–
2.0
1.0
2.0
1.0
–
-
–
–
6
3.2
1.7
3.2
1.6
0.7
0.9
0.8
1.1
–
–
-
–
-
0.9
1.2
1.1
1.5
V
A
A
A
A
LOWER GATE DRIVER CHARACTERISTICS
Driver voltage (V
DD
)
Low-side Driver Peak Gate Drive Current (Pull-
up)
(V
GL
- V
GNG
) = 2.5V
LSEL connected to
VDD
LSEL connected to
GND
Low-side Driver Peak Gate Drive Current (Pull-
down)
(V
GL
– V
GND
) = 2.5V
LSEL connected to
VDD
LSEL connected to
GND
Low-side Driver Pull-up Resistance
(V
DD
- V
GL
) = 50mV
LSEL connected to
VDD
LSEL connected to
GND
Low-side Driver Pull-down Resistance
(V
GL
– GND) = 50mV
LSEL connected to
VDD
LSEL connected to
GND
-
3.0
1.5
3.5
1.8
–
-
–
-
6.5
4.5
2.4
5.4
2.8
0.7
1.0
0.5
0.7
-
–
-
–
-
0.9
1.3
0.7
1.0
V
A
A
A
A
SWITCHING CHARACTERISTICS
GH rise time, t
RH
C
GH
= 3nF
HSEL connected to
BST
HSEL connected to
SW
–
-
5.3
10.5
8.5
16.5
ns
ns
FN6845 Rev 3.00
February 25, 2011
Page 5 of 13
京公网安备 11010802033920号
EEWORLD
