5.7 Soft Start Delay and Ramp Times ......................................................................................................................... 16
5.8 Switching Frequency and PLL .............................................................................................................................. 17
6.7 Voltage Tracking................................................................................................................................................... 27
6.8 Voltage Margining ................................................................................................................................................ 28
8. Ordering Information .................................................................................................................................................. 34
9. Related Documentation ............................................................................................................................................... 34
10. Revision History ........................................................................................................................................................ 35
2
FN6851.2
March 30, 2011
ZL2105
1. Electrical Characteristics
Table 1. Absolute Maximum Ratings
Voltage measured with respect to SGND. Operating beyond these limits may cause permanent damage to the device.
Functional operation beyond the Recommended Operating Conditions is not implied.
Parameter
DC Supply Voltage
Logic Supply Voltage
High Side Supply Voltage
High Side Boost Voltage
Switch Node Current
Internal Drive References
Internal 2.5 V Reference
Logic I/O Voltage
Pin
VDDP, VDDS, VDR
VDDL
BST
BST - SW
SW
VR, VRA
V25
EN, MGN, PG, SDA, SCL, SA,
SALRT, SS, DLY, SYNC,
VTRK, UVLO, V(0,1), ILIM,
VSEN, CFG
DGND - SGND
PGND - SGND
VR
VRA
V25
–
–
All
Soldering, 10 s
Comments
Optional
Value
-0.3 to 17
-0.3 to 6.5
-0.3 to 25
-0.3 to 8
4.5
-0.3 to 6.5
-0.3 to 3
-0.3 to 6.5
Unit
V
V
V
V
A
V
V
V
Sink or Source
Ground Differential
MOSFET Drive Reference
Current
Analog Reference Current
2.5 V Reference Current
Junction Temperature
Storage Temperature
Lead Temperature
±0.3
30
150
60
-55 to 150
-55 to 150
300
V
mA
mA
mA
°C
°C
°C
Table 2. Recommended Operating Conditions and Thermal Information
Symbol
Parameter
Input Supply Voltage Range, VDDP, VDDS
(See Figure 8)
Logic Supply Voltage Range, VDDL
Internal Driver Supply, VDR
Output Voltage Range
1
Operating Junction Temperature Range
Junction to Ambient Thermal Impedance
2
Junction to Case Thermal Impedance
3
Notes:
VDDS tied to VR, VRA
VR, VRA floating
VDDL (optional)
VDR
V
OUT
T
J
Θ
JA
Θ
JC
Min
4.5
5
3.0
10
0.54
-40
–
–
Typ
–
–
–
–
–
–
35
5
Max
5.5
14
5.5
14
5.5
125
–
–
Unit
V
V
V
V
V
°C
°C/W
°C/W
1. Includes margin
2. Θ
JA
is measured in free air with the device mounted on a multi-layer FR4 test board and the exposed metal pad
soldered to a low impedance ground plane using multiple vias.
3. For Θ
JC
, the “case” temperature is measured at the center of the exposed metal pad. See Figure 4 for thermal
derating.
3
FN6851.2
March 30, 2011
ZL2105
Table 3. Electrical Specifications
V
DDP
= V
DDS
= 12 V, T
A
= -40 C to 85 C unless otherwise noted. Typical values are at T
A
= 25 C.
Parameter
Input and Supply Characteristics
I
DDS
supply current
I
DDL
supply current
I
DDS
shutdown current
I
DDL
shutdown current
VR reference output voltage
VRA reference output voltage
V25 reference output voltage
Output Characteristics
Output Current
Output voltage adjustment range
1
Output voltage setpoint resolution
VSEN output voltage accuracy
VSEN input bias current
Soft start delay duration range
2
Soft start delay duration accuracy
Soft start ramp duration range
Soft start ramp duration accuracy
Logic Input/Output Characteristics
Logic input current
Logic input low, V
IL
Logic input OPEN (N/C)
Logic input high, V
IH
Logic output low, V
OL
Logic output high, V
OH
Tracking
VTRK input bias current
VTRK tracking accuracy
Notes:
Set using SS pin
Set using resistor or via I
2
C
f
SW
= 200 kHz, no load
f
SW
= 1 MHz, no load
f
SW
= 200 kHz, no load
f
SW
= 1 MHz, no load
EN = 0 V, VDDL tied to VRA,
No I
2
C/SMBus activity
EN = 0 V, VDDL = 5 V,
No I
2
C/SMBus activity
V
DD
> 5.5 V, I
VR
< 5 mA
V
DD
> 5.5 V, I
VRA
< 35 mA
I
V25
< 50 mA
–
–
–
–
–
–
4.5
4.5
2.25
–
0.6
–
–
-1
–
7
0.007
–
10
0
–
-250
–
–
2.0
–
2.25
–
- 100
2
5
8
10
0.7
225
5.2
5.2
2.5
–
–
10
±0.025
–
100
–
–
6
–
–
100
3
6
16
20
2
500
5.5
5.5
2.75
3
5.0
–
–
1
200
200
500
–
100
200
–
250
0.8
–
–
0.4
–
200
+ 100
mA
mA
mA
mA
mA
µA
V
V
V
A
V
mV
% FS
%
µA
ms
s
ms
ms
ms
µs
nA
V
V
V
V
V
µA
mV
Conditions
Min
(Note 3)
Typ
Max
(Note 3)
Unit
V
IN
> V
OUT
Set using resistors
Set using I
2
C/SMBus
Includes line, load, temp
VSEN = 5.5 V
Set using DLY pin or resistor
Set using I
2
C/SMBus
EN, SCL, SDA pins
Multi-mode logic pins
I
OL
≤ 4 mA
I
OH
≥ -2 mA
VTRK = 5.5 V
100% Tracking, V
OUT
- VTRK
–
1.4
–
–
–
110
–
1. Does not include margin
2. The device requires approximately 6 ms following an enable signal and prior to output ramp. The minimum
settable delay is 7 ms.
3. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
Table 3 is continued on the following page
4
FN6851.2
March 30, 2011
ZL2105
Table 3. Electrical Characteristics (continued)
V
DDP
= V
DDS
= 12 V, T
A
= -40 C to 85 C unless otherwise noted. Typical values are at T
A
= 25 C.
Parameter
Conditions
Min
(Note 3)
–
200
-5
150
-13
90
–
–
–
3.79
-2
–
0
–
–
–
–
0
0
–
0
–
0
–
–
5
0.2
–
–
1
–
-40
–
Typ
Max
(Note 3)
4.0
2000
5
–
13
–
180
140
130
13.2
2
–
100
2.5
–
–
–
200
500
–
110
–
115
–
–
60
4.5
–
–
32
–
125
–
Unit
Oscillator and Switching Characteristics
Sourcing or Sinking
Switch node current, I
SW
Switching frequency range
Predefined settings
Switching frequency set-point accuracy
Minimum SYNC pulse width
External clock source
Input clock frequency drift tolerance
Maximum duty cycle
I
SW
= 1 A, V
GS
= 4.7 V
R
DS(ON)
of High Side N-channel FETs
I
SW
=1A, V
GS
=8.5V, Charge Pump
R
DS(ON)
of Low Side N-channel FETs
I
SW
=1A, V
GS
=12V
Fault Protection Characteristics
UVLO threshold range
UVLO setpoint accuracy
UVLO hysteresis
UVLO delay
Power good low threshold
Power good high threshold
Power good hysteresis
Power good delay
VSEN undervoltage threshold
VSEN overvoltage threshold
VSEN undervoltage hysteresis
VSEN undervoltage/ overvoltage fault
response time
Peak current limit threshold
Current limit setpoint accuracy
Current limit shutdown delay
Thermal protection threshold (junction
temperature)
Thermal protection hysteresis
Notes:
Factory default
Configurable via I
2
C/SMBus
Using ILIM pin or via I
2
C/SMBus
Factory default
Configurable via I
2
C/SMBus
Factory default
Configurable via I
2
C/SMBus
Factory default
Configurable via I
2
C/SMBus
Factory default
Factory default
Factory default
Using pin-strap or resistor
1
Configurable via I
2
C/SMBus
Factory default
Configurable via I
2
C/SMBus
Factory default
Configurable via I
2
C/SMBus
3
–
–
–
–
–
125
123
114
–
–
3
–
–
90
115
5
–
–
85
–
115
–
5
16
–
–
±100
5
–
125
–
15
A
kHz
%
ns
%
%
mΩ
mΩ
mΩ
V
%
%
%
µs
% V
OUT
% V
OUT
%
ms
s
% V
OUT
% V
OUT
% V
OUT
% V
OUT
% V
O
µs
µs
A
mA
t
SW 2
t
SW 2
°C
°C
°C
1. Factory default Power Good delay is set to the same value as the soft start ramp time.
2. t
SW
= 1/f
SW
, where f
SW
is the switching frequency.
3. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
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