DATASHEET
3MHz Dual Step-Down Converters and Dual Low-Input
LDOs with I
2
C Compatible Interface
ISL9305
The ISL9305 is an integrated mini Power Management IC
(mini-PMIC) ideal for applications of powering low-voltage
microprocessor or multiple voltage rails with battery as input
sources, such as a single Li-ion or Li-Polymer. ISL9305
integrates two high-efficiency 3MHz synchronous step-down
converters (DCD1 and DCD2) and two low-input, low-dropout
linear regulators (LDO1 and LDO2).
The 3MHz PWM switching frequency allows the use of very small
external inductors and capacitors. Both step-down converters can
enter skip mode under light load conditions to further improve the
efficiency and maximize the battery life. For noise sensitive
applications, they can also be programmed through I
2
C interface
to operate in forced PWM mode regardless of the load current
condition. The I
2
C interface supports on-the-fly slew rate control of
the output voltage from 0.825V to 3.6V at 25mV/step size for
dynamic power saving. Each step-down converter can supply up to
800mA load current. The default output voltage can be set from
0.8V to V
IN
using external feedback resistors on the adjustable
version, or the ISL9305 can be ordered in factory pre-set voltage
options from 0.9V to 3.6V in 50mV step.
The ISL9305 also provides two 300mA low dropout (LDO)
regulators. The input voltage range is 1.5V to 5.5V allowing
them to be powered from one of the on-chip step-down
converters or directly from the battery. The default LDO
power-up output comes with factory pre-set fixed output
voltage options between 0.9V to 3.3V.
The ISL9305 is available in a 4mmx4mm 16 Ld TQFN package.
Features
• Dual 800mA, Synchronous Step-down Converters and Dual
300mA, General-purpose LDOs
• Input Voltage Range
- DCD1/DCD2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3V to 5.5V
- LDO1/LDO2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5V to 5.5V
• 400kb/s I
2
C-bus Series Interface Transfers the Control Data
Between the Host Controller and the ISL9305
• Adjustable Output Voltage
- VODCD1/VODCD2 . . . . . . . . . . . . . . . . . . . . . . . . 0.8V to V
IN
• Fixed Output I
2
C Programmability
- At 25mV/Step . . . . . . . . . . . . . . . . . . . . . . . . 0.825V to 3.6V
• LDO1/LDO2 Output Voltage I
2
C Programmability
- At 50mV/Step . . . . . . . . . . . . . . . . . . . . . . . . . . 0.9V to 3.6V
• 50μA I
Q
(Typ) with DCD1/DCD2 in Skip Mode; 20μA I
Q
(Typ)
for each Enabled LDO
• On-the-fly I
2
C Programming of DC/DC and LDO Output
Voltages
• DCD1/DCD2 I
2
C Programmable Skip Mode Under Light
Load or Forced Fixed Switching Frequency PWM Mode
• Small, Thin, 4mmx4mm TQFN Package
Applications
• Cellular Phones, Smart Phones
• PDAs, Portable Media Players, Portable Instruments
• Single Li-ion/Li-Polymer Battery-Powered Equipment
• DSP Core Power
Related Literature
•
ISL9305H
Data Sheet
•
AN1564
“ISL9305 and ISL9305H Evaluation Boards”
2.3V TO 5.5V
C
10
10µF
PG
VINDCD1
VINDCD2
SDAT
SCLK
C
2
1µF
VINLDO1
SW1
FB1
L
1
= 1.5µH
R
1
R
2
*
800mA
C
4
4.7µF
800mA
*
R
4
C
5
4.7µF
300mA
300mA
1.5V TO 5.5V
ISL9305
SW2
FB2
L
2
= 1.5µH
R
3
1.5V TO 5.5V
C
3
1µF
VOLDO1
VOLDO2
GNDDCD1 GNDDCD2 GNDLDO
VINLDO2
C
6
1µF
C
7
1µF
*Only for adjustable output version. For fixed output version, directly
connect the FB pin to the output of the buck converter.
FIGURE 1. TYPICAL APPLICATION DIAGRAM
February 9, 2015
FN7605.2
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Copyright Intersil Americas LLC 2010, 2014. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL9305
TABLE 1. TYPICAL APPLICATION PART LIST
PARTS
L1, L2
C1
C2, C3
C4, C5
C6, C7
R1, R2,
R3, R4
DESCRIPTION
Inductor
Input capacitor
Input capacitor
Output capacitor
Output capacitor
Resistor
MANUFACTURER
Sumida
Murata
Murata
Murata
Murata
Various
PART NUMBER
CDRH2D14NP-1R5
GRM21BR60J106KE19L
GRM185R60J105KE26D
GRM219R60J475KE01D
GRM185R60J105KE26D
SPECIFICATIONS
1.5µH/1.80A/50mΩ
10µF/6.3V
1µF/6.3V
4.7µF/6.3V
1µF/6.3V
1%, SMD, 0.1Ω
SIZE
3.0mmx3.0mmx1.55mm
0805
0603
0805
0603
0603
NOTE:
1. C4 and C5 are 10µF/6.3V for VODCD less than 1V.
Block Diagram
ANALOG/LOGIC
CIRCUIT INPUT
DCDPG
SHORT
CIRCUIT
PROTECTION
VINDCD1
10µF
SW1
DCD1
FB1
GNDDCD1
VINDCD2
SW2
DCD2
1.5µH
10µF
4.7µF
1.5µH
4.7µF
PGOOD WITH
1~200MS
DELAY TIME
BUCK CONVERTER
OVERCURRENT
PROTECTION
UVLO
VREF
OSC
FB2
GNDDCD2
BUCK CONVERTER
THERMAL
SHUTDOWN
LDO1
300mA
SDAT
SCLK
I
2
C
INTERFACE
LDO2
300mA
VINLDO1
1µF
VOLDO1
1µF
VINLDO2
1µF
VOLDO2
GNDLDO
1µF
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FN7605.2
February 9, 2015
ISL9305
Pin Configuration
ISL9305
(16 LD 4x4 TQFN)
TOP VIEW
GNDCDC1
GNDDCD2
14
16
SW1
15
SW2
13
12
VINDCD2
11
FB2
10
DCDPG
VINDCD1
1
FB1
2
E-PAD
SCLK
3
SDAT
4
5
6
7
8
9 GNDLDO
VOLDO1
VINLDO1
VOLDO2
Pin Descriptions
PIN
NUMBER
(TQFN)
1
2
3
4
5
6
7
8
9
10
NAME
VINDCD1
FB1
SCLK
SDAT
VINLDO1
VOLDO1
VOLDO2
VINLDO2
GNDLDO
DCDPG
DESCRIPTION
Input voltage for buck converter DCD1 and it also serves as the power supply pin for the whole internal digital/ analog
circuits.
Feedback pin for DCD1, connect external voltage divider resistors between DCDC1 output, this pin and ground. For
fixed output versions, connect this pin directly to the DCD1 output.
I
2
C interface clock pin.
I
2
C interface data pin.
Input voltage for LDO1.
Output voltage of LDO1.
Output voltage of LDO2.
Input voltage for LDO2.
Power ground for LDO1 and LDO2.
The DCDPG pin is an open-drain output to indicate the state of the DCD1/DCD2 output voltages. When both DCD1
and DCD2 are enabled, the output is released to be pulled high by an external pull-up resistor if both converter
voltages are within the power-good range. The pin will be pulled low if either DCD is outside their range. When only
one DCD is enabled, the state of the enabled DCD’s output will define the state of the DCDPG pin. The DCDPG state
can be programmed for a delay of up to 200ms before being released to rise high. The programming range is
1ms~200ms through the I
2
C interface.
Feedback pin for DCD2, connect external voltage divider resistors between DCD2 output, this pin and ground. For
fixed output versions, connect this pin directly to the DCD2 output.
Input voltage for buck converter DCD2.
Switching node for DCD2, connect to one terminal of the inductor.
Power ground for DCD2.
Power ground for DCD1.
Switching node for DCD1, connect to one terminal of the inductor.
Exposed Pad. Connect to system ground.
11
12
13
14
15
16
E-pad
FB2
VINDCD2
SW2
GNDDCD2
GNDDCD1
SW1
E-pad
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VINLDO2
FN7605.2
February 9, 2015
ISL9305
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
ISL9305IRTAANLZ-T
ISL9305IRTBCNLZ-T
ISL9305IRTBFNCZ-T
ISL9305IRTWBNLZ-T
ISL9305IRTWCLBZ-T
ISL9305IRTWCNLZ-T
ISL9305IRTWCNYZ-T
ISL9305IRTWLNCZ-T
ISL9305IRTAANLZEV1Z
ISL9305IRTBCNLZEV1Z
ISL9305IRTBFNCZEV1Z
ISL9305IRTWBNLZEV1Z
ISL9305IRTWCLBZEV1Z
ISL9305IRTWCNLZEV1Z
ISL9305IRTWCNYZEV1Z
ISL9305IRTWLNCZEV1Z
NOTES:
1. Please refer to
TB347
for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for
ISL9305.
For more information on MSL please see techbrief
TB363.
PART MARKING
9305I AANLZ
9305I BCNLZ
9305I BFNCZ
9305I WBNLZ
9305I WCLBZ
9305I WCNLZ
9305I WCNYZ
9305I WLNCZ
Evaluation Board
Evaluation Board
Evaluation Board
Evaluation Board
Evaluation Board
Evaluation Board
Evaluation Board
Evaluation Board
FBSEL
DCD1
(V)
Adj
1.5
1.5
1.2
1.2
1.2
1.2
1.2
FBSEL
DCD2
(V)
Adj
1.8
2.5
1.5
1.8
1.8
1.8
2.9
SLV
LDO1
(V)
3.3
3.3
3.3
3.3
2.9
3.3
3.3
3.3
SLV
LDO2
(V)
2.9
2.9
1.8
2.9
1.5
2.9
0.9
1.8
TEMP. RANGE
(°C)
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
PACKAGE
Tape and Reel
(Pb-free)
16 Ld TQFN
16 Ld TQFN
16 Ld TQFN
16 Ld TQFN
16 Ld TQFN
16 Ld TQFN
16 Ld TQFN
16 Ld TQFN
PKG.
DWG. #
L16.4x4G
L16.4x4G
L16.4x4G
L16.4x4G
L16.4x4G
L16.4x4G
L16.4x4G
L16.4x4G
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FN7605.2
February 9, 2015
ISL9305
Absolute Maximum Ratings
(Refer to ground)
SW1, SW2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.5V to 6.5V
FB1, FB2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 3.6V
GNDDCD1, GNDDCD2, GNDLDO. . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V
All other pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
ESD Ratings
Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . .3.5kV
Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . 225V
Charged Device Model (Tested per JESD22-C101D) . . . . . . . . . . . 2.2kV
Latch Up (Tested per JESD78B, Class II, Level A) . . . . . . . . . . . . . . . 100mA
Thermal Information
Thermal Resistance (Typical)
JA
(°C/W)
JC
(°C/W)
16 Ld TQFN Package (Notes 4, 5) . . . . . . .
40.2
5
Maximum Junction Temperature Range . . . . . . . . . . . . . .-40°C to +150°C
Recommended Junction Temperature Range . . . . . . . . .-40°C to +125°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see
TB493
Recommended Operating Conditions
VINDCD1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3V to 5.5V
VINDCD2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3V to VINDCD1
VINLDO1 and VINLDO2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5V to VINDCD1
DCD1 and DCD2 Output Current . . . . . . . . . . . . . . . . . . . . . 0mA to 800mA
LDO1 and LDO2 Output Current . . . . . . . . . . . . . . . . . . . . . . 0mA to 300mA
Operating Ambient Temperature . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4.
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief
TB379.
5.
JC
, “case temperature” location is at the center of the exposed metal pad on the package underside.
Unless otherwise noted, all parameter limits are guaranteed over the recommended operating conditions
and the typical specifications are measured at the following conditions: T
A
= +25°C, VINDCD1 = 3.6V, VINDCD2 = 3.3V. For LDO1 and LDO2,
VINLDOx = VOLDOx + 0.5V to 5.5V with VINLDOx always no higher than VINDCD1, L1 = L
2
= 1.5µH, C
1
= 10µF, C
4
= C
5
= 4.7µF,
C
2
= C
3
= C
6
= C
7
= 1µF, I
OUT
= 0A for DCD1, DCD2, LDO1 and LDO2 (see Figure 1 on page 1 for more details). Boldface limits apply over the operating
temperature range, -40°C to +85°C.
PARAMETER
VINDCD1, VINDCD2 Voltage Range
VINDCD1, VINDCD2 Undervoltage
Lockout Threshold
Quiescent Supply Current on VINDCD1
V
UVLO
I
VIN1
I
VIN2
I
VIN3
I
VIN4
I
VIN5
Rising
Falling
Only DCD1 enabled, no load and no switching
on DCD1
Only DCD1 and LDO1 enabled, with no load and
no switching on DCD1
Both DCD1 and DCD2 enabled, no load and no
switching on both DCD1 and DCD2
Only LDO1 and LDO2 enabled
DCD1, DCD2, LDO1 and LDO2 are enabled,
with no load and no switching on both DCD1
and DCD2
Only one DCD in forced PWM mode, no load
VINDCD1 = 5.5V, DCD1, DCD2, LDO1 and LDO2
are disabled through I
2
C interface,
VINDCD1 = 4.2V
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
2.3
-
1.9
-
-
-
-
-
TYP
-
2.2
2.1
40
65
50
75
100
MAX
(Note 6)
5.5
2.3
-
60
95
75
100
130
UNIT
V
V
V
µA
µA
µA
µA
µA
Electrical Specifications
I
VIN6
Shutdown Supply Current
I
SD
-
-
4
0.15
7.5
5
mA
µA
Thermal Shutdown
Thermal Shutdown Hysteresis
DCD1 AND DCD2
FB1, FB2 Regulation Voltage
FB1, FB2 Bias Current
Output Voltage Accuracy
Line Regulation
Maximum Output Current
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V
FB
I
FB
FB = 0.75V
V
IN
= V
O
+ 0.5V to 5.5V (minimal 2.3V),
1mA load
V
IN
= V
O
+ 0.5V to 5.5V (minimal 2.3V)
-
-
0.785
-
-3
-
800
155
30
0.8
0.001
-
0.1
-
-
-
0.815
-
+3
-
-
°C
°C
V
µA
%
%/V
mA
FN7605.2
February 9, 2015
5
Embedded System
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