LF
BUK9K18-40E
23 April 2013
PA
K
56D
Dual N-channel TrenchMOS logic level FET
Product data sheet
1. General description
Dual logic level N-channel MOSFET in a LFPAK56D package using TrenchMOS
technology. This product has been designed and qualified to AEC Q101 standard for use
in high performance automotive applications.
2. Features and benefits
•
•
•
•
Q101 compliant
Repetitive avalanche rated
Suitable for thermally demanding environments due to 175 °C rating
True logic level gate with V
GS(th)
> 0.5 V @ 175 °C
3. Applications
•
•
•
•
•
12 V Automotive systems
Motors, lamps and solenoid control
Start-stop micro-hybrid applications
Transmission control
Ultra high performance power switching
4. Quick reference data
Table 1.
Symbol
V
DS
I
D
P
tot
R
DSon
Quick reference data
Parameter
drain-source voltage
drain current
total power dissipation
Conditions
T
j
≥ 25 °C; T
j
≤ 175 °C
V
GS
= 5 V; T
mb
= 25 °C;
Fig. 1
T
mb
= 25 °C;
Fig. 2
V
GS
= 5 V; I
D
= 10 A; T
j
= 25 °C;
Fig. 12
Min
-
-
-
Typ
-
-
-
Max
40
30
38
Unit
V
A
W
Static characteristics FET1 and FET2
drain-source on-state
resistance
gate-drain charge
-
17.1
19.5
mΩ
Dynamic characteristics FET1 and FET2
Q
GD
I
D
= 10 A; V
DS
= 32 V; V
GS
= 10 V;
T
j
= 25 °C;
Fig. 14
-
3
-
nC
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NXP Semiconductors
BUK9K18-40E
Dual N-channel TrenchMOS logic level FET
5. Pinning information
Table 2.
Pin
1
2
3
4
5
6
7
8
Pinning information
Symbol Description
S1
G1
S2
G2
D2
D2
D1
D1
source1
gate1
source2
gate2
drain2
drain2
drain1
drain1
1
2
3
4
S1
G1
S2
G2
mbk725
Simplified outline
8
7
6
5
Graphic symbol
D1 D1
D2 D2
LFPAK56D (SOT1205)
6. Ordering information
Table 3.
Ordering information
Package
Name
BUK9K18-40E
LFPAK56D
Description
Plastic single ended surface mounted package (LFPAK56D); 8
leads
Version
SOT1205
Type number
7. Marking
Table 4.
Marking codes
Marking code
91840E
Type number
BUK9K18-40E
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
DS
V
DGR
V
GS
Parameter
drain-source voltage
drain-gate voltage
gate-source voltage
Conditions
T
j
≥ 25 °C; T
j
≤ 175 °C
R
GS
= 20 kΩ; T
j
≥ 25 °C; T
j
≤ 175 °C
T
j
≤ 175 °C; DC
T
j
≤ 175 °C; Pulsed
I
D
drain current
T
mb
= 25 °C; V
GS
= 5 V;
Fig. 1
T
mb
= 100 °C; V
GS
= 5 V;
Fig. 1
I
DM
BUK9K18-40E
Min
-
-
-10
[1][2]
Max
40
40
10
15
30
24
124
Unit
V
V
V
V
A
A
A
2 / 13
-15
-
-
-
peak drain current
T
mb
= 25 °C; pulsed; t
p
≤ 10 µs;
Fig. 4
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved
Product data sheet
23 April 2013
NXP Semiconductors
BUK9K18-40E
Dual N-channel TrenchMOS logic level FET
Symbol
P
tot
T
stg
T
j
T
sld(M)
I
S
I
SM
E
DS(AL)S
Parameter
total power dissipation
storage temperature
junction temperature
peak soldering temperature
Conditions
T
mb
= 25 °C;
Fig. 2
Min
-
-55
-55
-
Max
38
175
175
260
Unit
W
°C
°C
°C
Source-drain diode FET1 and FET2
source current
peak source current
T
mb
= 25 °C
pulsed; t
p
≤ 10 µs; T
mb
= 25 °C
I
D
= 30 A; V
sup
≤ 40 V; V
GS
= 5 V;
T
j(init)
= 25 °C;
Fig. 3
-
-
30
124
A
A
Avalanche Ruggedness FET1 and FET2
non-repetitive drain-source
avalanche energy
[1]
[2]
[3]
[4]
40
I
D
(A)
30
[3][4]
-
22
mJ
Accumulated Pulse duration up to 50 hours delivers zero defect ppm
Significantly longer life times are achieved by lowering T
j
and or V
GS
.
Refer to application note AN10273 for further information
Single-pulse avalanche rating limited by maximum junction temperature of 175 °C
003aaj625
120
P
der
(%)
80
03aa16
20
40
10
0
0
50
100
150
T
mb
(° C)
200
0
0
50
100
150
T
mb
(°C)
200
Fig. 1.
Continuous drain current as a function of
mounting base temperature
Fig. 2.
Normalized total power dissipation as a
function of mounting base temperature
BUK9K18-40E
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved
Product data sheet
23 April 2013
3 / 13
NXP Semiconductors
BUK9K18-40E
Dual N-channel TrenchMOS logic level FET
I
AL
(A)
10
3
003aaj668
10
2
10
(1)
1
(2)
(3)
10
-1
10
-2
10
-3
10
-2
10
-1
1
t
AL
(ms)
10
Fig. 3.
Single-pulse and repetitive avalanche rating; avalanche current as a function of avalanche time, FET1 and
FET2
I
D
(A)
10
3
003aaj627
10
2
Limit R
DSon
= V
DS
/ I
D
t
p
= 10 us
10
DC
100 us
1 ms
1
10 ms
100 ms
10
-1
10
-1
1
10
V
DS
(V)
10
2
Fig. 4.
Safe operating area; continuous and peak drain current as a function of drain-source voltage
9. Thermal characteristics
Table 6.
Symbol
R
th(j-mb)
Thermal characteristics
Parameter
thermal resistance
from junction to
mounting base
Conditions
Fig. 5
Min
-
Typ
-
Max
3.96
Unit
K/W
BUK9K18-40E
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved
Product data sheet
23 April 2013
4 / 13
NXP Semiconductors
BUK9K18-40E
Dual N-channel TrenchMOS logic level FET
Symbol
R
th(j-a)
Parameter
thermal resistance
from junction to
ambient
Conditions
Minimum footprint; mounted on a
printed circuit board
Min
-
Typ
95
Max
-
Unit
K/W
10
Z
th(j-mb)
(K/W)
1
003aaj683
δ
= 0.5
0.2
0.1
0.05
0.02
10
-1
P
δ=
t
p
T
single shot
10
-2
10
-6
t
p
t
T
10
-5
10
-4
10
-3
10
-2
10
-1
t
p
(s)
1
Fig. 5.
Transient thermal impedance from junction to mounting base as a function of pulse duration
10. Characteristics
Table 7.
Symbol
V
(BR)DSS
Characteristics
Parameter
drain-source
breakdown voltage
gate-source threshold
voltage
Conditions
I
D
= 250 µA; V
GS
= 0 V; T
j
= -55 °C
I
D
= 250 µA; V
GS
= 0 V; T
j
= 25 °C
I
D
= 1 mA; V
DS
= V
GS
; T
j
= 25 °C;
Fig. 10; Fig. 11
I
D
= 1 mA; V
DS
= V
GS
; T
j
= 175 °C;
Fig. 10; Fig. 11
I
D
= 1 mA; V
DS
= V
GS
; T
j
= -55 °C;
Fig. 10; Fig. 11
I
DSS
drain leakage current
V
DS
= 40 V; V
GS
= 0 V; T
j
= 175 °C
V
DS
= 40 V; V
GS
= 0 V; T
j
= 25 °C
I
GSS
gate leakage current
V
GS
= -10 V; V
DS
= 0 V; T
j
= 25 °C
V
GS
= 10 V; V
DS
= 0 V; T
j
= 25 °C
R
DSon
drain-source on-state
resistance
V
GS
= 5 V; I
D
= 10 A; T
j
= 25 °C;
Fig. 12
V
GS
= 5 V; I
D
= 10 A; T
j
= 175 °C;
Fig. 12; Fig. 13
-
-
-
-
-
-
-
0.02
2
2
17.1
34.37
500
1
100
100
19.5
39.2
µA
µA
nA
nA
mΩ
mΩ
-
-
2.45
V
0.5
-
-
V
Min
36
40
1.4
Typ
-
-
1.7
Max
-
-
2.1
Unit
V
V
V
Static characteristics FET1 and FET2
V
GS(th)
BUK9K18-40E
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved
Product data sheet
23 April 2013
5 / 13
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