DATASHEET
ISL6115A
12V Power Distribution Controllers
This fully featured hot swap power controller targets
+12V applications. The ISL6115A with its integrated
charge pump has a higher (6.5V vs 5V) gate drive
than its sister part the ISL6115 making this part an
immediate efficiency improvement replacement.
This IC features programmable overcurrent (OC)
detection, current regulation (CR) with time delay to
latch-off and soft-start.
The current regulation level is set by 2 external
resistors; R
ISET
sets the CR Vth and the other is a
low ohmic sense resistor across, which the CR Vth is
developed. The CR duration is set by an external
capacitor on the CTIM pin, which is charged with a
20µA current once the CR Vth level is reached. The
IC then quickly pulls down the GATE output latching
off the pass FET.
FN6855
Rev 1.00
April 23, 2010
Features
• HOT SWAP Single Power Distribution Control for
+12V
• Overcurrent Fault Isolation
• Programmable Current Regulation Level
• Programmable Current Regulation Time to
Latch-Off
• Rail-to-Rail Common Mode Input Voltage Range
• Enhanced Internal Charge Pump Drives N-Channel
MOSFET gate to 6.5V above IC bias.
• Undervoltage and Overcurrent Latch Indicators
• Adjustable Turn-On Ramp
• Protection During Turn-On
• Two Levels of Overcurrent Detection Provide Fast
Response to Varying Fault Conditions
• 1µs Response Time to Dead Short
• Pb-Free (RoHS Compliant)
Applications
• Power Distribution Control
• Hot Plug Components and Circuitry
Application Circuits - High Side Controller
+
LOAD
-
1
2
3
4
8
ISL6115A
PWRON
7
6
OC
5
PGOOD
+V SUPPLY TO BE CONTROLLED
+12V
FN6855 Rev 1.00
April 23, 2010
Page 1 of 10
ISL6115A
Simplified Block Diagram
V
DD
+
I
SET
-
+
+
-
I
SEN
V
REF
ENABLE
12V
UV
8V
-
+
-
POR
QN R
R
Q
S
PWRON
PGOOD
UV DISABLE
OC
GATE
10µA
18V
+
-
-
+
WOCLIM
ENABLE
20µA
CLIM
7.5k
+
-
1.86V
20µA
RISING
EDGE
PULSE
V
DD
FALLING
EDGE
DELAY
CTIM
+
-
V
SS
18V
Pin Configuration
ISL6115A
(8 LD SOIC)
TOP VIEW
ISET
ISEN
GATE
VSS
1
2
3
4
8 PWRON
7 PGOOD
6 CTIM
5 VDD
Ordering Information
PART NUMBER
(Notes 2, 3)
ISL6115AIBZ
ISL6115AIBZ-T (Notes 1, )
ISL6115ACBZ
ISL6115ACBZ-T (Notes 1, )
ISL6115AEVAL1Z
NOTES:
1. Please refer to
TB347
for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for
ISL6115A.
For more information on MSL please
see techbrief
TB363.
PART
MARKING
6115A IBZ
6115A IBZ
6115A CBZ
6115A CBZ
Evaluation Platform
TEMPERATURE
RANGE (°C)
-40 to +85
-40 to +85
0 to +70
0 to +70
PACKAGE
(Pb-free)
8 Ld SOIC
8 Ld SOIC
8 Ld SOIC
8 Ld SOIC
PKG.
DWG. #
M8.15
M8.15
M8.15
M8.15
FN6855 Rev 1.00
April 23, 2010
Page 2 of 10
ISL6115A
Pin Descriptions
PIN
NO.
1
2
3
SYMBOL
ISET
ISEN
GATE
FUNCTION
Current Set
Current Sense
External FET Gate
Drive Pin
Chip Return
Chip Supply
Current Limit Timing
Capacitor
Power Good Indicator
12V chip supply. This can be either connected directly to the +12V rail supplying the
switched load voltage or to a dedicated V
SS
+12V supply.
Connect a capacitor from this pin to ground. This capacitor determines the time delay
between an overcurrent event and chip output shutdown (current limit time-out). The
duration of current limit time-out is equal to 93k x C
TIM
.
Indicates that the voltage on the ISEN pin is satisfactory. PGOOD is driven by an open
drain N-Channel MOSFET and is pulled low when the output voltage (VISEN) is less than
the UV level for the particular IC.
PWRON is used to control and reset the chip. The chip is enabled when PWRON pin is
driven high to a maximum of 5V or is left open. Do not drive this input >5V. After a
current limit time-out, the chip is reset by a low level signal applied to this pin. This input
has 20µA pull-up capability.
DESCRIPTION
Connect to the low side of the current sense resistor through the current limiting set resistor.
This pin functions as the current limit programming pin.
Connect to the more positive end of sense resistor to measure the voltage drop across this
resistor.
Connect to the gate of the external N-Channel MOSFET. A capacitor from this node to
ground sets the turn-on ramp. At turn-on this capacitor will be charged to V
DD
+6.5V
by an 14µA current source.
4
5
6
VSS
VDD
CTIM
7
PGOOD
8
PWRON
Power-ON
FN6855 Rev 1.00
April 23, 2010
Page 3 of 10
ISL6115A
Absolute Maximum Ratings
T
A
= +25°C
V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +16V
GATE . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V
DD
+ 8V
ISEN, PGOOD, PWRON, CTIM, ISET . . . -0.3V to V
DD
+ 0.3V
Thermal Information
Thermal Resistance (Typical, Note 4)
JA
(°C/W)
8 Ld SOIC Package . . . . . . . . . . . . . . . . . . .
98
Maximum Junction Temperature (Plastic Package) . . +150°C
Maximum Storage Temperature Range . . . -65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
V
DD
Supply Voltage Range
Temperature Range (T
A
) . .
ESD
Human Body Model . . . .
Machine Model . . . . . . .
. . . . . . . . . . . . . . . +12V ±15%
. . . . . . . . . . . . -40°C to +85°C
. . . . . . . . . . . . . . . . . . . . 2.5kV
. . . . . . . . . . . . . . . . . . . . 250V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
4.
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief
TB379 for details.
5. All voltages are relative to GND, unless otherwise specified.
Electrical Specifications
PARAMETER
CURRENT CONTROL
ISET Current Source
ISET Current Source
Current Limit Amp Offset Voltage
Current Limit Amp Offset Voltage
GATE DRIVE
GATE Response Time to Severe OC
V
DD
= 12V, T
A
= T
J
= full temperature range, Unless Otherwise Specified.
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6) UNITS
I
ISET_ft
I
ISET_pt
Vio_ft
Vio_pt
T
J
= +15°C to +55°C
V
ISET
- V
ISEN
V
ISET
- V
ISEN,
T
J
= +15°C to
+55°C
17
19
-4.5
-2
20
20
0
0
22
21
4.5
2
µA
µA
mV
mV
pd_woc_amp
pd_oc_amp
I
GATE
OC_GATE_I_4V
V
GATE
to 10.8V
V
GATE
to 10.8V
V
GATE
to = 6V
Overcurrent
-
-
10.8
45
-
8.9
100
600
14
82
0.8
9.6
V
DD
+
6.5V
-
-
16.7
124
-
10.2
-
ns
ns
µA
mA
A
V
V
GATE Response Time to Overcurrent
GATE Turn-On Current
GATE Pull-Down Current
GATE Pull-Down Current (Note 6)
Undervoltage Threshold
GATE High Voltage
BIAS
V
DD
Supply Current
V
DD
POR Rising Threshold
V
DD
POR Falling Threshold
V
DD
POR Threshold Hysteresis
Maximum PWRON Pull-Up Voltage
PWRON Pull-Up Voltage
PWRON Rising Threshold
PWRON Hysteresis
PWRON Pull-Up Current
WOC_GATE_I_4V Severe Overcurrent
12V
UV_VTH
12VG
GATE Voltage
V
DD
+
5.7V
I
VDD
V
DD_POR_L2H
V
DD_POR_H2L
V
DD_POR_HYS
PWRN_PUV
PWRN_V
PWR_Vth
PWR_hys
PWRN_I
VDD Low to High
VDD High to Low
V
DD_POR_L2H -
V
DD_POR_H2L
Maximum External Pull-up
Voltage
PWRON Pin Open
-
7
6.9
0.1
-
2.5
1.1
125
12.6
3
8.4
8.1
0.3
5
3.2
1.7
170
17
3.9
9
8.7
0.5
-
-
2.35
250
24
mA
V
V
V
V
V
V
mV
µA
FN6855 Rev 1.00
April 23, 2010
Page 4 of 10
ISL6115A
Electrical Specifications
PARAMETER
V
DD
= 12V, T
A
= T
J
= full temperature range, Unless Otherwise Specified.
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6) UNITS
CURRENT REGULATION DURATION/POWER GOOD
C
TIM
Charging Current
C
TIM
Fault Pull-Up Current (Note 6)
Current Limit Time-Out Threshold
Voltage
Power Good Pull Down Current
NOTES:
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested.
C
TIM
_Vth
PG_Ipd
CTIM Voltage
V
OUT
= 0.5V
C
TIM
_ichg0
V
CTIM
= 0V
17.2
-
1.6
-
20.5
20
1.8
8
25
-
2.1
-
µA
mA
V
mA
Description and Operation
The ISL6115A is targeted for +12V single power supply
distribution control for generic hot swap switching
applications.
This ICs features a highly accurate programmable
current regulation (CR) level with programmable time
delay to latch-off, and programmable soft-start
turn-on ramp all set with a minimum of external
passive components. It also includes severe OC
protection that immediately shuts down the MOSFET
switch should a rapid load current transient such as
with a dead short cause the CR Vth to exceed the
programmed level by 150mV. Additionally, it has an
UV indicator and an OC latch indicator. The
functionality of the PGOOD feature is enabled once
the IC is biased, monitoring and reporting any UV
condition on the ISEN pin.
Upon initial power-up, the IC can either isolate the
voltage supply from the load by holding the external
N-Channel MOSFET switch off or apply the supply rail
voltage directly to the load for true hot swap capability.
The PWRON pin must be pulled low for the device to
isolate the power supply from the load by holding the
external N-Channel MOSFET off. With the PWRON pin
held high or floating the IC will be in true hot swap
mode. In both cases the IC turns on in a soft-start
mode protecting the supply rail from sudden inrush
current.
At turn-on, the external gate capacitor of the
N-Channel MOSFET is charged with a 11µA current
source resulting in a programmable ramp (soft-start
turn-on). The internal ISL6115A charge pump supplies
the gate drive for the 12V supply switch driving that
gate to ~V
DD
+6.5V. Load current passes through the
external current sense resistor. When the voltage
across the sense resistor exceeds the user
programmed CR voltage threshold value, (see Table 1
for R
ISET
programming resistor value and resulting
nominal current regulation threshold voltage, V
CR
)
the controller enters its current regulation mode. At
this time, the time-out capacitor, on CTIM pin is
charged with a 20µA current source and the controller
enters the current limit time to latch-off period. The
length of the current limit time to latch-off duration is
set by the value of a single external capacitor (see
Table 2) for C
TIM
capacitor value and resulting
nominal current limited time-out to latch-off duration
placed from the CTIM pin (pin 6) to ground. The
programmed current level is held until either the OC
event passes or the time-out period expires. If the
former is the case then the N-Channel MOSFET is fully
enhanced and the C
TIM
capacitor is discharged. Once
C
TIM
charges to ~1.8V signaling that the time-out
period has expired, an internal latch is set whereby
the FET gate is quickly pulled to 0V turning off the
N-Channel MOSFET switch, isolating the faulty load.
TABLE 1. R
ISET
PROGRAMMING RESISTOR VALUE
R
ISET
RESISTOR
10k
4.99k
2.5k
1.25k
NOTE: Nominal Vth = R
ISET
x 20µA.
TABLE 2. C
TIM
CAPACITOR VALUE
C
TIM
CAPACITOR
0.022µF
0.047µF
0.1µF
NOMINAL CURRENT LIMITED
PERIOD
2ms
4.4ms
9.3ms
NOMINAL CR VTH
200mV
100mV
50mV
25mV
NOTE: Nominal time-out period = C
TIM
x 93k.
This IC responds to a severe overcurrent load (defined
as a voltage across the sense resistor >150mV over
the OC Vth set point) by immediately driving the
N-Channel MOSFET gate to 0V in about 10µs. The gate
voltage is then slowly ramped up turning on the
N-Channel MOSFET to the programmed current
regulation level; this is the start of the time-out period.
FN6855 Rev 1.00
April 23, 2010
Page 5 of 10
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