CMX138A datasheet, PDF - EEWORLD Datasheet

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CMX138A: DescriptionProgrammable Audio Scrambler; File Size1MB，73 Pages; ManufacturerCML Microcircuits; Websitehttp://www.cmlmicro.com/

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CMX138A Overview

Programmable Audio Scrambler

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CML Microcircuits

COMMUNICA

TION SEMICONDUCTORS

CMX138A

Audio Scrambler and

Sub-Audio Signalling

Processor

D/138A/4 October 2014

CMX138A: Audio Scrambler and Sub-Audio Signalling Processor with Auxiliary

System Clock, ADC and DAC for use in Analogue Radio Systems

Features



Programmable Audio Scrambler



Concurrent Audio/Signalling Operations



Full Audio-band Processing:

Pre and De-emphasis, Compandor,

Scrambler and Selectable 2.55/3 kHz Filters



Auxiliary ADC and Auxiliary DAC



C-BUS Serial Interface to Host µController



Two Analogue Inputs (Mic or Discriminator)

DAC Output

ADC Input

3.0V to 3.6V



Selectable Audio Processing Order



Sub-audio Signalling: CTCSS, DCS



Auxiliary System Clock Output



Tx Output for Single-point Modulation



Low-power (3.0V to 3.6V) Operation



Flexible Powersave Modes



Available in 28-pin TSSOP Package

Modulator

Discriminator

GPIO

CMX138A

Audio Scrambler

and

Sub-Audio Processor

Built on

FirmASIC

technology

C-BUS

Host

µC

System Clock 1

Reference Clock

Brief Description

The CMX138A is a half-duplex, audio scrambler and sub-audio signalling processor IC for Analogue Two-

way Radio applications. This makes it a suitable device for the leisure radio markets (FRS, MURS,

PMR446 and GMRS).

This device provides a user programmable frequency inversion audio scrambler, companding and pre/de-

emphasis – performing simultaneous processing of Sub-audio and In-band signalling.

Other features include an auxiliary ADC channel and an auxiliary DAC interface (with optional RAMDAC,

to facilitate transmitter power ramping).

The device has flexible powersaving modes and is available in a 28-pin (E1) TSSOP package.



2014 CML Microsystems Plc

Audio Scrambler and Sub-Audio Signalling Processor

CMX138A

CONTENTS

Section

Page

Brief Description ...................................................................................................................... 1

History ...................................................................................................................................... 5

Block Diagram .......................................................................................................................... 6

Signal List................................................................................................................................. 7

4.1

Signal Definitions .......................................................................................................... 8

External Components.............................................................................................................. 9

5.1

PCB Layout Guidelines and Power Supply Decoupling .............................................. 11

General Description............................................................................................................... 12

Detailed Descriptions ............................................................................................................ 13

7.1

Xtal Frequency............................................................................................................ 13

7.2

Host Interface ............................................................................................................. 13

7.2.1 C-BUS Operation ................................................................................................. 13

7.3

Device Control ............................................................................................................ 15

7.3.1 Signal Routing ...................................................................................................... 15

7.3.2 Mode Control ........................................................................................................ 16

7.4

Audio Functions .......................................................................................................... 17

7.4.1 Audio Receive Mode ............................................................................................ 17

7.4.2 Audio Transmit Mode ........................................................................................... 19

7.4.3 Audio Compandor ................................................................................................ 23

7.5

Sub-audio Signalling ................................................................................................... 25

7.5.1 Receiving and Decoding CTCSS Tones .............................................................. 27

7.5.2 Receiving and Decoding DCS Codes .................................................................. 28

7.5.3 Transmit CTCSS Tone ......................................................................................... 30

7.5.4 Transmit DCS Code ............................................................................................. 30

7.6

In-band Signalling – User Tones ................................................................................ 30

7.6.1 Receiving and Decoding In-band Tone ................................................................ 30

7.6.2 Transmitting In-band Tone ................................................................................... 31

7.7

Auxiliary ADC Operation ............................................................................................. 31

7.8

Auxiliary DAC/RAMDAC Operation ............................................................................ 32

7.9

Digital System Clock Generator.................................................................................. 33

7.9.1 Main Clock Operation........................................................................................... 33

7.9.2 System Clock Operation ...................................................................................... 33

7.10

GPIO ........................................................................................................................... 34

7.11

Signal Level Optimisation ........................................................................................... 34

7.11.1 Transmit Path Levels ........................................................................................... 34

7.11.2 Receive Path Levels............................................................................................. 34

C-BUS Register Summary..................................................................................................... 35

8.1.1 Interrupt Operation ............................................................................................... 36

8.1.2 General Notes ...................................................................................................... 36

Configuration Guide .............................................................................................................. 37

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D/138A/4



2014 CML Microsystems Plc

Audio Scrambler and Sub-Audio Signalling Processor

CMX138A

C-BUS Register Details .............................................................................................. 37

9.1.1 Reset Operations ................................................................................................. 38

9.1.2 General Reset - $01 write .................................................................................... 38

9.1.3 AuxADC and TX MOD Mode - $A7 write ............................................................. 40

9.1.4 AuxDAC Control/Data - $A8 write ........................................................................ 40

9.1.5 AuxADC Data - $A9 read ..................................................................................... 41

9.1.6 System Clk PLL Data - $AB write ........................................................................ 42

9.1.7 System Clk REF - $AC write ................................................................................ 42

9.1.8 Analogue Input Gain - $B0 write .......................................................................... 43

9.1.9 Analogue Output Gain - $B1 write........................................................................ 44

9.1.10 AuxADC Threshold Data - $B5 write.................................................................... 45

9.1.11 Power Down Control - $C0 write .......................................................................... 45

9.1.12 Mode Control – $C1 write..................................................................................... 46

9.1.13 Audio Control – $C2 write .................................................................................... 46

9.1.14 Tx In-band Tone - $C3 write ................................................................................ 47

9.1.15 Status – $C6 read ................................................................................................ 47

9.1.16 Programming – $C8 write .................................................................................... 48

9.1.17 Scrambler Inversion Frequency – $CB write ........................................................ 48

9.1.18 Tone Status - $CC read ....................................................................................... 48

9.1.19 Audio Tone - $CD: 16-bit write ............................................................................. 49

9.1.20 Interrupt Mask - $CE write ................................................................................... 52

9.1.21 Reserved - $CF write ........................................................................................... 52

9.2

Programming Register Operation ............................................................................... 53

9.2.1 Program Block 0 – reserved ................................................................................ 54

9.2.2 Program Block 1 – In-band Tone Setup: .............................................................. 54

9.2.3 Program Block 2 – CTCSS and DCS Setup ........................................................ 55

9.2.4 Program Block 3 – AuxDAC, RAMDAC and Clock Control: ................................ 57

9.2.5 Program Block 4 – Gain and Offset Setup: .......................................................... 58

9.2.6 Initialisation of the Programming Register Blocks: ............................................... 62

10 Application Notes .................................................................................................................. 63

11 Performance Specification ................................................................................................... 63

11.1

Electrical Performance ............................................................................................... 63

11.1.1 Absolute Maximum Ratings ................................................................................. 63

11.1.2 Operating Limits ................................................................................................... 63

11.1.3 Operating Characteristics..................................................................................... 64

11.1.4 Parametric Performance ...................................................................................... 69

11.2

C-BUS Timing ............................................................................................................. 72

11.3

Packaging ................................................................................................................... 73

9.1

Table

Table 1

Table 2

Table 3

Table 4

Table 5

Table 6

Page

Definition of Power Supply and Reference Voltages.......................................................... 8

Xtal/clock Frequency Settings for Program Block 3 ......................................................... 13

DCS Codes and CTCSS Tones ....................................................................................... 26

DCS Modulation Modes ................................................................................................... 28

DCS 23 Bit Codes ............................................................................................................ 29

In-band Tone .................................................................................................................... 31

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2014 CML Microsystems Plc

Page 3

D/138A/4

Audio Scrambler and Sub-Audio Signalling Processor

CMX138A

Table 7 C-BUS Registers .............................................................................................................. 35

Table 8 Reset Operations ............................................................................................................. 38

Table 9 Voice Level Attenuation.................................................................................................... 50

Table 10 Voice Level Attenuation.................................................................................................. 50

Table 11 RAMDAC Values ............................................................................................................ 57

Table 12 Voice Level Attenuation.................................................................................................. 59

Figure

Page

Figure 1 Block Diagram ................................................................................................................... 6

Figure 2 CMX138A Recommended External Components ............................................................ 9

Figure 3 CMX138A Power Supply Connections and De-coupling ................................................ 11

Figure 4 C-BUS Transactions ....................................................................................................... 14

Figure 5 Signal Routing ................................................................................................................. 16

Figure 6 Rx 25kHz Channel Audio Filter Frequency Response .................................................... 18

Figure 7 De-emphasis Curve for TIA/EIA-603 Compliance .......................................................... 18

Figure 8 Tx Channel Audio Filter Response and Template (ETSI) ............................................... 20

Figure 9 Tx Channel Audio Filter Response and Template (TIA) ................................................. 20

Figure 10 Audio Frequency Pre-emphasis .................................................................................... 21

Figure 11 Expandor Transient Response ..................................................................................... 23

Figure 12 Compressor Transient Response ................................................................................. 24

Figure 13 Low Pass Sub-audio Band Filter for CTCSS and DCS ................................................. 27

Figure 14 AuxADC IRQ Operation ................................................................................................ 32

Figure 15 Digital Clock Generation Schemes ............................................................................... 33

Figure 16 Default Tx Audio Filter Line-up ..................................................................................... 61

Figure 17 Default Rx Audio Filter Line-up ..................................................................................... 61

Figure 18 C-BUS Timing ............................................................................................................... 72

Figure 19 Mechanical Outline of 28-pin TSSOP (E1) ................................................................... 73

It is always recommended that you check for the latest product datasheet version from the CML website:

[www.cmlmicro.com].



2014 CML Microsystems Plc

Page 4

D/138A/4

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