ESMT
Flash
PRODUCT LIST
Parameters
V
CC
V
CCQ1
Width
Frequency
Internal ECC Correction
Transfer Rate
Loading Throughput
Power-up Ready Time
Max Reset Busy Time
Note:
1. V
CCQ
should be the same as V
CC
.
2. x2 PROGRAM operation is not defined.
Values
3.3V
3.3V
x1, x2
2
, x4
104MHz
1-bit
10ns
104MT/s
1ms (maximum value)
1ms (maximum value)
F50L512M41A
3.3V 512 Mbit
SPI-NAND Flash Memory
FEATURES
Voltage Supply: 3.3V (2.7V~3.6V)
Organization
- Memory Cell Array: (64M + 2M) x 8bit
- Data Register: (2K + 64) x 8bit
Automatic Program and Erase
- Page Program: (2K + 64) Byte
- Block Erase: (128K + 4K) Byte
Page Read Operation
- Page Size: (2K + 64) Byte
- Read from Cell to Register with Internal ECC: 100us
Memory Cell: 1bit/Memory Cell
Support SPI-Mode 0 and SPI-Mode 3
1
Fast Write Cycle Time
- Program time:400us
- Block Erase time: 4ms
Note:
1. Mode 0: CPOL = 0, CPHA = 1; Mode 3: CPOL = 1, CPHA = 1
Hardware Data Protection
- Program/Erase Lockout During Power Transitions
Reliable CMOS Floating Gate Technology
- Internal ECC Requirement: 1bit/512Byte
- Endurance: 100K Program/Erase cycles
- Data Retention: 10 years
Command Register Operation
NOP: 4 cycles
OTP Operation
Bad-Block-Protect
ORDERING INFORMATION
Product ID
F50L512M41A -104RAG
Speed
104MHz
Package
8-contact LGA
8x6mm
Comments
Pb-free
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2014
Revision: 1.1
1/36
ESMT
GENERAL DESCRIPTION
The serial electrical interface follows the industry-standard serial
peripheral interface (SPI), providing a cost-effective non-volatile
memory storage solution in systems where pin count must be
kept to a minimum. The device is a 512Mb SLC SPI-NAND
Flash memory device based on the standard parallel NAND
Flash, but new command protocols and registers are defined for
SPI operation. It is also an alternative to SPI-NOR, offering
superior write performance and cost per bit over SPI-NOR.
The command set resembles common SPI-NOR command set,
modified to handle NAND-specific functions and new features.
New features include user-selectable internal ECC. With internal
ECC enabled, ECC code is generated internally when a page is
written to the memory array. The ECC code is stored in the
spare area of each page. When a page is read to the cache
register, the ECC code is calculated again and compared with
the stored value. Errors are corrected if necessary. The device
either outputs corrected data or returns an ECC error status.
F50L512M41A
The memory is divided into blocks that can be erased
independently so it is possible to preserve valid data while old
data is erased. The device contains 512 blocks, composed by 64
pages consisting in two NAND structures of 32 series connected
Flash cells. Each page consists 2112-Byte and is further divided
into a 2048-Byte data storage area with a separate 64-Byte
spare area. The 64-Byte area is typically used for memory and
error management.
The pins serve as the ports for signals. The device has six signal
lines plus V
CC
and ground (GND, V
SS
). The signal lines are SCK
(serial clock), SI (command and data input), SO (response and
data output), and control signals CS#, HOLD#, WP#.
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2014
Revision: 1.1
2/36
ESMT
PIN CONFIGURATION (TOP VIEW)
8-Contact LGA
(LGA 8C, 8mmx6 mm Body, 1.27mm Contact Pitch)
F50L512M41A
CS#
SO (IO
1
)
WP# (IO
2
)
V
SS
1
2
3
4
8
7
6
5
V
CC
HOLD# (IO
3
)
SCK
SI (IO
0
)
Pin Description
Pin Name
Functions
Chip Select (Input)
The device is activated
1
/deactivated
2
as CS# is driven LOW/HIGH.
After power-on, the device requires a falling-edge on CS# before any command can be
written. The device goes to standby mode when no PROGRAM, ERASE, or WRITE
STATUS REGISTER operation is in progress.
Hold (Input) / IO
3
(Input/Output)
Hold pauses any serial communication with the device without deselecting it
3
. When driven
LOW, SO is at high impedance (Hi-Z), and all inputs in SI and SCK are ignored; CS# also
should be driven LOW.
HOLD# must not be driven during x4 operation.
Write Protect (Input) / IO
2
(Input/Output)
WP# is driven LOW to prevent overwriting the block-lock bits (BP0, BP1, and BP2) if the
block register write disable (BRWD) bit is set
4
.
WP# must not be driven during x4 operation.
Serial Clock (Input)
SCK provides serial interface timing.
Address, commands, and data in SI are latched on the rising edge of SCK.
Output (data in SO) is triggered after the falling-edge of SCK.
The clock is valid only when the device is active.
5
Serial Data Input (Input) / IO
0
(Input/Output)
SI transfers data serially into the device. Device latches addresses, commands, and program
data in SI on the rising-edge of SCK.
SI must not be driven during x2 or x4 READ operation.
Serial Data Output (Output) / IO
1
(Input/Output)
SO transfers data serially out of the device on the falling-edge of SCK.
SO must not be driven during x2 or x4 PROGRAM operation.
Power
V
CC
is the power supply for device.
Ground
No Connection
Not internally connected.
CS#
HOLD# / IO
3
WP# / IO
2
SCK
SI / IO
0
SO / IO
1
V
CC 6
V
SS 6
NC
Note:
1. CS# places the device in active power mode.
2. CS# deselects the device and places SO at high impedance.
3. It means HOLD# input doesn’t terminate any READ, PROGRAM, or ERASE operation currently in progress.
4. If the BRWD bit is set to 1 and WP# is LOW, the block protect bits can’t be altered.
5. SI and SO can be triggered only when the clock is valid.
6. Connect all V
CC
and V
SS
pins of each device to common power supply outputs. Do not leave V
CC
or V
SS
disconnected.
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2014
Revision: 1.1
3/36
ESMT
BLOCK DIAGRAM
F50L512M41A
ARRAY ORGANIZATION
Array Address
Data Bits
1 byte
2
nd
byte
3
rd
byte
4
th
byte
5
th
byte
st
0
A
0
A
8
A
12
A
20
*L
1
A
1
A
9
A
13
A
21
*L
2
A
2
A
10
A
14
A
22
*L
3
A
3
A
11
A
15
A
23
*L
4
A
4
*L
A
16
A
24
*L
5
A
5
*L
A
17
A
25
*L
6
A
6
*L
A
18
A
26
*L
7
A
7
*L
A
19
*L
*L
Address
Column Address
Column Address
Row Address
Row Address
Dummy Address
Note:
Column Address: Starting Address of the Register.
*L must be set to “Low”.
The device ignores any additional input of address cycles than required.
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2014
Revision: 1.1
4/36
ESMT
COMMAND SET
Function
BLOCK ERASE
1
F50L512M41A
Op Code
D8h
0Fh
1Fh
04h
06h
02h
2
Address Byte
3
1
1
0
0
2
2
2
2
3
3
2
2
2
1
0
Dummy Byte
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
Data Bytes
0
1
1
0
0
1 to 2112
1 to 2112
1 to 2112
1 to 2112
0
0
1 to 2112
1 to 2112
1 to 2112
2
0
GET FEATURE
SET FEATURE
WRITE DISABLE
WRITE ENABLE
PROGRAM LOAD
PROGRAM LOAD x4
PROGRAM LOAD RANDOM
DATA
PROGRAM LOAD RANDOM
2
32h
84h
34h
10h
13h
03h, 0Bh
3Bh
6Bh
9Fh
FFh
DATA x4
PROGRAM EXECUTE
PAGE READ
READ FROM CACHE
READ FROM CACHE x2
2
READ FROM CACHE x4
3
READ ID
RESET
Note:
1. Refer to Feature Register.
2. Command/Address is 1-bit input per clock period, data is 4-bit input/output per clock period.
3. Address is 00h to get JEDEC ID
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2014
Revision: 1.1
5/36
Analogue and Mixed Signal
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