NCP59749
3.0 A, Dual-Rail Very
Low‐Dropout Linear
Regulator with
Programmable Soft‐Start
The NCP59749 is dual−rail very low dropout voltage regulator that
is capable of providing an output current in excess of 3.0 A with a
dropout voltage of 120 mV typ. at full load current. The devices are
stable with ceramic and any other type of output capacitor
≥
2.2
mF.
This series contains adjustable output voltage version with output
voltage down to 0.8 V. Internal protection features consist of built−in
thermal shutdown and output current limiting protection.
User−programmable Soft−Start and Power Good pins are available.
The NCP59749 is available in QFN20 5x5 package.
Features
http://onsemi.com
QFN20
CASE 485DB
PIN CONNECTIONS
OUT
1
20
19
OUT
OUT
OUT
NC
FB
18
17
16
11 12 13 14 15
GND
EN
NC
NC
SS
NC
4
NC
3
NC
2
IN
5
IN
IN
IN
PG
BIAS
6
7
8
9
10
•
•
•
•
•
•
•
•
•
•
•
Output Current in Excess of 3.0 A
V
IN
Range: 0.8 V to 5.5 V
V
BIAS
Range: 2.7 V to 5.5 V
Output Voltage Range: 0.8 V to 3.6 V
Dropout Voltage: 120 mV at 3 A
Programmable Soft Start
Open Drain Power Good Output
Fast Transient Response
Stable with Any Type of Output Capacitor
≥
2.2
mF
Current Limit and Thermal Shutdown Protection
These are Pb−Free Devices
GND
QFN20, 5x5, 0.65P
MARKING DIAGRAM
1
XXXXXXXX
XXXXXXXX
AWLYYWWG
G
QFN20
XXXXX = Specific Device Code
A
= Assembly Location
L/WL
= Wafer Lot
Y/YY
= Year
W/WW = Work Week
G
= Pb-Free Package
(Note: Microdot may be in either location)
Applications
•
Consumer and Industrial Equipment Point of Load Regulation
•
FPGA, DSP and Logic Power Supplies
•
Switching Power Supply Post Regulation
NCP59749
Figure 1. Typical Application Schematic
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 9 of this data sheet.
©
Semiconductor Components Industries, LLC, 2014
March, 2014
−
Rev. 0
1
Publication Order Number:
NCP59749/D
NCP59749
Figure 2. Simplified Schematic Block Diagram
Table 1. PIN FUNCTION DESCRIPTION
Name
IN
EN
SS
BIAS
PG
QFN−20
5−8
11
15
10
9
Unregulated input to the device.
Enable pin. Driving this pin high enables the regulator. Driving this pin low puts the regulator into
shutdown mode. This pin must not be left floating.
Soft-Start pin. A capacitor connected on this pin to ground sets the start-up time. If this pin is left
floating, the regulator output soft-start ramp time is typically 200
ms.
Bias input voltage for error amplifier, reference, and internal control circuits.
Power-Good (PG) is an open-drain, active-high output that indicates the status of V
OUT
. When V
OUT
exceeds the PG trip threshold, the PG pin goes into a high-impedance state. When V
OUT
is below this
threshold the pin is driven to a low-impedance state. A pull-up resistor from 10 kW to 1 MW should be
connected from this pin to a supply up to 5.5 V. The supply can be higher than the input voltage.
Alternatively, the PG pin can be left floating if output monitoring is not necessary.
This pin is the feedback connection to the center tap of an external resistor divider network that sets the
output voltage. This pin must not be left floating.
Regulated output voltage. A small capacitor (total typical capacitance
≥
2.2
mF,
ceramic) is needed from
this pin to ground to assure stability.
Description
FB
OUT
NC
GND
PAD/TAB
16
1, 18−20
2−4, 13, 14, 17 No connection. This pin can be left floating or connected to GND to allow better thermal contact to the
top-side plane.
12
Ground
Should be soldered to the ground plane for increased thermal performance
http://onsemi.com
2
NCP59749
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameter
Input Voltage Range
Input Voltage Range
Enable Voltage Range
Power-Good Voltage Range
PG Sink Current
SS Pin Voltage Range
Feedback Pin Voltage Range
Output Voltage Range
Maximum Output Current
Output Short Circuit Duration
Continuous Total Power Dissipation
Maximum Junction Temperature
Storage Junction Temperature Range
ESD Capability, Human Body Model (Note 2)
ESD Capability, Machine Model (Note 2)
P
D
T
JMAX
T
STG
ESD
HBM
ESD
MM
Symbol
V
IN
V
BIAS
V
EN
V
PG
I
PG
V
SS
V
FB
V
OUT
I
OUT
Value
−0.3
to +6
−0.3
to +6
−0.3
to +6
−0.3
to +6
0 to +1.5
−0.3
to +6
−0.3
to +6
−0.3
to (V
IN
+ 0.3)
≤
6
Internally Limited
Indefinite
See Thermal Characteristics Table and Formula
+125
−55
to +150
2000
200
°C
°C
V
V
Unit
V
V
V
V
mA
V
V
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
2. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per EIA/JESD22-A114
ESD Machine Model tested per EIA/JESD22-A115
Latch-up Current Maximum Rating tested per JEDEC standard: JESD78.
Table 3. THERMAL CHARACTERISTICS
Rating
Thermal Characteristics, QFN20, 5x5, 0.65P package
Thermal Resistance, Junction−to−Ambient (Note 5)
Thermal Resistance, Junction−to−Case (bottom) (Note 6)
R
qJA
R
qJC
30.5
4.1
°C/W
°C/W
Symbol
Value
Unit
3. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
4. Thermal data are derived by thermal simulations based on methodology specified in the JEDEC JESD51 series standards. The following
assumptions are used in the simulations:
−
This data was generated with only a single device at the center of a high−K (2s2p) board with 3 in x 3 in copper area which follows the
−
JEDEC51.7 guidelines.
−
The exposed pad is connected to the PCB ground layer through a 4x4 thermal via array. Vias are 0.3 mm diameter, plated.
−
Each of top and bottom copper layers has a dedicated pattern for 20% copper coverage.
5. The junction−to−ambient thermal resistance under natural convection is obtained in a simulation on a high−K board, following the JEDEC51.7
guidelines with assumptions as above, in an environment described in JESD51−2a.
6. The junction−to−case (bottom) thermal resistance is obtained by simulating a cold plate test on the IC exposed pad. Test description can
be found in the ANSI SEMI standard G30−88.
Table 4. RECOMMENDED OPERATING CONDITIONS
(Note 7)
Rating
Input Voltage
Bias Voltage
Junction Temperature
Symbol
V
IN
V
BIAS
T
J
Min
V
OUT
+ V
DO
2.7
−40
Max
5.5
5.5
125
Unit
V
V
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
7. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
http://onsemi.com
3
NCP59749
(At V
EN
= 1.1 V, V
IN
= V
OUT
+ 0.3 V, C
BIAS
= 0.1
mF,
C
SS
= 1 nF, C
IN
= C
OUT
= 10
mF,
I
OUT
= 50 mA, V
BIAS
= 5.0 V, T
J
=
−40°C
to
+125°C, unless otherwise noted. Typical values are at T
J
= +25°C.)
Symbol
V
IN
V
BIAS
UVLO
V
REF
V
OUT
Parameter
Input Voltage Range
Bias Pin Voltage Range
Undervoltage Lock-out
Internal Reference (Adj.)
Output Voltage Range
Accuracy (Note 1)
V
OUT
/V
IN
V
OUT
/I
OUT
V
DO
Line Regulation
Load Regulation
V
IN
Dropout Voltage (Note 2)
V
BIAS
Dropout Voltage (Note 2)
I
CL
I
BIAS
I
SHDN
I
FB
PSRR
Current Limit
Bias Pin Current
Shutdown Supply Current (I
GND
)
Feedback Pin Current
Power-supply Rejection
(V
IN
to V
OUT
)
1 kHz, I
OUT
= 1.5 A, V
IN
= 1.8 V,
V
OUT
= 1.5 V
300 kHz, I
OUT
= 1.5 A, V
IN
= 1.8 V,
V
OUT
= 1.5 V
Power-supply Rejection
(V
BIAS
to V
OUT)
1 kHz, I
OUT
= 1.5 A, V
IN
= 1.8 V,
V
OUT
= 1.5 V
300 kHz, I
OUT
= 1.5 A, V
IN
= 1.8 V,
V
OUT
= 1.5 V
Noise
t
STRT
I
SS
V
EN, HI
V
EN, LO
V
EN, HYS
V
EN, DG
I
EN
V
IT
V
HYS
V
PG, LO
I
PG, LKG
TSD
Output Noise Voltage
Minimum Startup Time
Soft-start Charging Current
Enable Input High Level
Enable Input Low Level
Enable Pin Hysteresis
Enable Pin Deglitch Time
Enable Pin Current
PG Trip Threshold
PG Trip Hysteresis
PG Output Low Voltage
PG Leakage Current
Thermal Shutdown Temperature
I
PG
= 1 mA (Sinking), V
OUT
<
V
IT
V
PG
= 5.25 V, V
OUT
> V
IT
Shutdown, temperature increasing
Reset, temperature decreasing
0.1
+165
+140
V
EN
= 5 V
V
OUT
decreasing
85
100 Hz to 100 kHz, l
OUT
= 3 A
R
LOAD
for I
OUT
= 1.0 A, C
SS
= open
V
SS
= 0.4 V
1.1
0
50
20
0.1
90
3
0.3
1
1
94
V
EN
≤
0.4 V
-1
V
BIAS
rising
Hysteresis
T
J
= +25°C
V
IN
= 5 V, I
OUT
= 3.0 A
V
OUT
+ 2.2 V < V
BIAS
< 5.5 V,
50 mA < l
OUT
< 3.0 A
V
OUT (NOM)
+ 0.3 < V
IN
< 5.5 V
50mA < I
OUT
< 3.0 A
I
OUT
=
3.0 A,
V
BIAS
- V
OUT (NOM)
≥
3.25 V (Note 3)
I
OUT =
3.0 A, V
IN
= V
BIAS
V
OUT
= 80% x V
OUT (NOM)
3.8
Test Conditions
Min
V
OUT
+V
DO
2.7
1.2
0.798
V
REF
-2
±0.5
0.03
0.09
120
1.31
4.6
1
1
0.15
60
30
50
30
25 x V
OUT
200
0.44
5.5
0.4
mV
RMS
ms
mA
V
V
mV
ms
mA
%V
OUT
%V
OUT
V
mA
°C
dB
280
1.75
6.0
2
50
1
1.6
0.4
0.802
Typ
Max
5.5
5.5
1.9
0.806
3.6
+2
Unit
V
V
V
V
V
%
%/V
%/A
mV
V
A
mA
mA
mA
dB
Table 5. ELECTRICAL CHARACTERISTICS
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. Adjustable devices tested at V
REF
; external resistor tolerance is not taken into account.
2. Dropout is defined as the voltage from the input to V
OUT
when V
OUT
is 3% below nominal.
3. 3.25 V is a test condition of this device and can be adjusted by referring to Figure 8.
http://onsemi.com
4
NCP59749
At T
J
= +25°C, V
IN
= V
OUT(TYP)
+ 0.3 V, V
BIAS
= 5 V, I
OUT
= 50 mA, V
EN
= V
IN
,
C
IN
= 1
mF,
C
BIAS
= 4.7
mF,
and C
OUT
= 10
mF,
unless otherwise noted.
0.20
0.15
CHANGE IN V
OUT
(%)
CHANGE IN V
OUT
(%)
0.10
0.05
0
+25°C
−40°C
0.5
0.4
0.3
0.2
0.1
0
−0.1
−0.2
−0.3
−0.4
−0.5
+25°C
−40°C
+125°C
TYPICAL CHARACTERISTICS
+125°C
−0.05
−0.10
−0.15
−0.20
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
V
IN
−
V
OUT
(V)
V
BIAS
−
V
OUT
(V)
Figure 3. V
IN
Line Regulation
0.5
0.4
CHANGE IN V
OUT
(%)
0.2
0.1
0
−0.1
−0.2
−0.3
−0.4
−0.5
−40°C
0
10
20
30
40
50
CHANGE IN V
OUT
(%)
0.3
+125°C
+25°C
0.5
0.4
0.3
0.2
0.1
0
−0.1
−0.2
−0.3
−0.4
−0.5
Figure 4. V
BIAS
Line Regulation
+125°C
+25°C
−40°C
0
0.5
1.0
1.5
2.0
2.5
3.0
I
OUT
, OUTPUT CURRENT (mA)
I
OUT
, OUTPUT CURRENT (A)
Figure 5. Load Regulation
V
DO
(V
IN
−
V
OUT
) DROPOUT VOLTAGE (mV)
V
DO
(V
IN
−
V
OUT
) DROPOUT VOLTAGE (mV)
120
100
80
60
40
20
0
−40°C
+125°C
+25°C
500
450
400
350
300
250
200
150
100
50
0
0.5
1.0
Figure 6. Load Regulation
I
OUT
= 3 A
+25°C
+125°C
−40°C
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0
0.5
1.0
1.5
2.0
2.5
3.0
I
OUT
, OUTPUT CURRENT (A)
V
BIAS
−
V
OUT
(V)
Figure 7. V
IN
Dropout Voltage vs. I
OUT
and
Temperature T
J
Figure 8. V
IN
Dropout Voltage vs. (V
BIAS
−
V
OUT
) and Temperature T
J
http://onsemi.com
5
京公网安备 11010802033920号
EEWORLD
