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NSS40300MZ4_13

Description
Bipolar Power Transistors 40 V, 3.0 A, Low VCE(sat) PNP Transistor
File Size83KB,6 Pages
ManufacturerON Semiconductor
Websitehttp://www.onsemi.cn
Download Datasheet View All

NSS40300MZ4_13 Overview

Bipolar Power Transistors 40 V, 3.0 A, Low VCE(sat) PNP Transistor

NSS40300MZ4
Bipolar Power Transistors
40 V, 3.0 A, Low V
CE(sat)
PNP Transistor
ON Semiconductor’s e
2
PowerEdge family of low V
CE(sat)
transistors are surface mount devices featuring ultra low saturation
voltage (V
CE(sat)
) and high current gain capability. These are designed
for use in low voltage, high speed switching applications where
affordable efficient energy control is important.
Typical applications are DC−DC converters and power management
in portable and battery powered products such as cellular and cordless
phones, PDAs, computers, printers, digital cameras and MP3 players.
Other applications are low voltage motor controls in mass storage
products such as disc drives and tape drives. In the automotive
industry they can be used in air bag deployment and in the instrument
cluster. The high current gain allows e
2
PowerEdge devices to be
driven directly from PMU’s control outputs, and the Linear Gain
(Beta) makes them ideal components in analog amplifiers.
Features
http://onsemi.com
PNP TRANSISTOR
3.0 AMPERES
40 VOLTS, 2.0 WATTS
C 2, 4
B1
E3
Schematic
4
3
SOT−223
CASE 318E
STYLE 1
1 2
Complement to NSS40301MZ4 Series
NSV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q101
Qualified and PPAP Capable
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
MAXIMUM RATINGS
(T
C
= 25°C unless otherwise noted)
Rating
Collector−Emitter Voltage
Collector−Base Voltage
Emitter−Base Voltage
Base Current − Continuous
Collector Current − Continuous
Collector Current − Peak
Total Power Dissipation
Total P
D
@ T
A
= 25°C (Note 1)
Total P
D
@ T
A
= 25°C (Note 2)
Operating and Storage Junction
Temperature Range
Symbol
V
CEO
V
CB
V
EB
I
B
I
C
I
CM
P
D
2.0
0.80
T
J
, T
stg
– 55 to + 150
°C
Value
40
40
6.0
1.0
3.0
5.0
Unit
Vdc
Vdc
Vdc
Adc
Adc
Adc
W
A
Y
W
40300
G
1
MARKING DIAGRAM
AYW
40300G
= Assembly Location
Year
= Work Week
= Specific Device Code
= Pb−Free Package
PIN ASSIGNMENT
4
C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Mounted on 1” sq. (645 sq. mm) Collector pad on FR−4 bd material.
2. Mounted on 0.012” sq. (7.6 sq. mm) Collector pad on FR−4 bd material.
B
1
C
2
E
3
Top View Pinout
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
©
Semiconductor Components Industries, LLC, 2013
1
September, 2013 − Rev. 3
Publication Order Number:
NSS40300MZ4/D
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