DP
AK
BUJ303AD
NPN power transistor
Rev. 1 — 2 September 2011
Product data sheet
1. Product profile
1.1 General description
High voltage, high speed planar passivated NPN power switching transistor in a SOT428
(DPAK) surface mountable plastic package.
1.2 Features and benefits
Fast switching
Low thermal resistance
Surface mountable package
Very high voltage capability
Very low switching and conduction
losses
1.3 Applications
DC-to-DC converters
High frequency electronic lighting
ballasts
Inverters
Motor control systems
1.4 Quick reference data
Table 1.
Symbol
I
C
P
tot
V
CESM
Quick reference data
Parameter
collector current
total power dissipation
collector-emitter peak
voltage
DC current gain
Conditions
see
Figure 1;
see
Figure 2;
see
Figure 4
T
mb
≤
25 °C; see
Figure 3
V
BE
= 0 V
Min
-
-
-
Typ
-
-
-
Max
5
80
Unit
A
W
1000 V
Static characteristics
h
FE
I
C
= 5 mA; V
CE
= 5 V;
T
mb
= 25 °C; see
Figure 11
I
C
= 500 mA; V
CE
= 5 V;
T
mb
= 25 °C; see
Figure 11
10
14
22
25
30
35
NXP Semiconductors
BUJ303AD
NPN power transistor
2. Pinning information
Table 2.
Pin
1
2
3
mb
Pinning information
Symbol Description
B
C
E
C
base
collector
[1]
emitter
mounting base;
connected to collector
2
1
3
mb
B
E
sym123
Simplified outline
Graphic symbol
C
SOT428 (DPAK)
[1]
it is not possible to make a connection to pin 2 of the SOT428 (DPAK) package.
3. Ordering information
Table 3.
Ordering information
Package
Name
BUJ303AD
DPAK
Description
plastic single-ended surface-mounted package (DPAK);
3 leads (one lead cropped)
Version
SOT428
Type number
4. Limiting values
Table 4.
Symbol
V
CESM
V
CEO
I
C
I
CM
I
B
I
BM
P
tot
T
stg
T
j
Limiting values
Parameter
collector-emitter peak voltage
collector-emitter voltage
collector current
peak collector current
base current
peak base current
total power dissipation
storage temperature
junction temperature
T
mb
≤
25 °C; see
Figure 3
Conditions
V
BE
= 0 V
I
B
= 0 A
see
Figure 1;
see
Figure 2;
see
Figure 4
Min
-
-
-
-
-
-
-
-65
-
Max
1000
500
5
10
2
4
80
150
150
Unit
V
V
A
A
A
A
W
°C
°C
In accordance with the Absolute Maximum Rating System (IEC 60134).
BUJ303AD
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 2 September 2011
2 of 14
NXP Semiconductors
BUJ303AD
NPN power transistor
12
I
C
(A)
V
CC
L
C
8
V
CL(CE)
probe point
4
003aag028
I
Bon
V
BB
L
B
DUT
001aab999
0
0
400
800
1200
V
CEclamp
(V)
Fig 1.
Test circuit for reverse bias safe operating area
120
P
der
(%)
80
Fig 2.
Reverse bias safe operating area
001aab993
40
0
0
40
80
120
T
mb
(°C)
160
Fig 3.
Normalized total power dissipation as a function of mounting base temperature
BUJ303AD
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 2 September 2011
3 of 14
NXP Semiconductors
BUJ303AD
NPN power transistor
10
2
I
C
(A)
I
CMmax
I
Cmax
(1)
003aag029
10
duty cycle = 0.01
II
(3)
t
p
= 10 µs
1
(2)
100 µs
1 ms
10 ms
DC
III
(3)
10
-1
I
(3)
10
-2
1
10
10
2
V
CEclamp
(V)
10
3
(1) P
tot
maximum and P
tot
peak maximum lines.
(2) Second breakdown limits.
(3) I = Region of permissible DC operation.
II = Extension for repetitive pulse operation.
III = Extension during turn-on in single transistor converters provided that R
BE
≤
100
Ω
and t
p
≤
0.6
μs.
Fig 4.
Forward bias safe operating area for Tmb
≤
25 °C
BUJ303AD
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 2 September 2011
4 of 14
NXP Semiconductors
BUJ303AD
NPN power transistor
5. Thermal characteristics
Table 5.
Symbol
R
th(j-mb)
R
th(j-a)
Thermal characteristics
Parameter
thermal resistance from
junction to mounting base
thermal resistance from
junction to ambient
Conditions
see
Figure 5
printed circuit board (FR4)
mounted; minimum footprint
Min
-
-
Typ
-
75
Max
1.56
-
Unit
K/W
K/W
10
Z
th(j-mb)
(K/W)
1
δ
= 0.5
0.2
0.1
10
−1
0.05
0.02
0.01
t
p
T
P
tot
001aab998
δ
=
t
p
T
t
10
−2
10
−5
10
−4
10
−3
10
−2
10
−1
1
t
p
(s)
10
Fig 5.
Transient thermal impedance from junction to mounting base as a function of pulse width
BUJ303AD
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 2 September 2011
5 of 14
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