DIGITAL AUDIO MOSFET
Features
IRFI4019H-117P
Key Parameters
h
150
80
13
4.1
2.5
150
V
m:
nC
nC
Ω
°C
PD - 97074A
Integrated Half-Bridge Package
Reduces the Part Count by Half
Facilitates Better PCB Layout
Key Parameters Optimized for Class-D
Audio Amplifier Applications
Low R
DS(ON)
for Improved Efficiency
Low Qg and Qsw for Better THD and
Improved Efficiency
Low Qrr for Better THD and Lower EMI
Can Delivery up to 200W per Channel into
8Ω Load in Half-Bridge Configuration
Amplifier
Lead-Free Package
V
DS
R
DS(ON)
typ. @ 10V
Q
g
typ.
Q
sw
typ.
R
G(int)
typ.
T
J
max
G1
S1/D2
G2
D1
S2
TO-220 Full-Pak 5 PIN
G1, G2
D1, D2
S1, S2
Description
Gate
Drain
Source
This Digital Audio MosFET Half-Bridge is specifically designed for Class D audio amplifier applications. It
consists of two power MosFET switches connected in half-bridge configuration. The latest process is used
to achieve low on-resistance per silicon area. Furthermore, Gate charge, body-diode reverse recovery, and
internal Gate resistance are optimized to improve key Class D audio amplifier performance factors such
as efficiency, THD and EMI. These combine to make this Half-Bridge a highly efficient, robust and reliable
device for Class D audio amplifier applications.
Absolute Maximum Ratings
h
Parameter
V
DS
V
GS
I
D
@ T
C
= 25°C
I
D
@ T
C
= 100°C
I
DM
E
AS
P
D
@T
C
= 25°C
P
D
@T
C
= 100°C
T
J
T
STG
Drain-to-Source Voltage
Gate-to-Source Voltage
Continuous Drain Current, V
GS
@ 10V
Continuous Drain Current, V
GS
@ 10V
Pulsed Drain Current
c
Single Pulse Avalanche Energyd
Power Dissipation
f
Power Dissipation
f
Linear Derating Factor
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case)
Mounting torque, 6-32 or M3 screw
300
10lbxin (1.1Nxm)
Max.
150
±20
8.7
6.2
34
77
18
7.2
0.15
-55 to + 150
Units
V
A
mJ
W
W/°C
°C
Thermal Resistance
h
Parameter
R
θJC
R
θJA
Junction-to-Case
f
Junction-to-Ambient
f
Typ.
–––
–––
Max.
6.9
65
Units
Notes
through
are on page 2
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1
8/22/06
IRFI4019H-117P
Electrical Characteristics @ T
J
= 25°C (unless otherwise specified)
h
Parameter
BV
DSS
∆ΒV
DSS
/∆T
J
R
DS(on)
V
GS(th)
∆V
GS(th)
/∆T
J
I
DSS
I
GSS
g
fs
Q
g
Q
gs1
Q
gs2
Q
gd
Q
godr
Q
sw
R
G(int)
t
d(on)
t
r
t
d(off)
t
f
C
iss
C
oss
C
rss
C
oss
L
D
L
S
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Gate Threshold Voltage Coefficient
Drain-to-Source Leakage Current
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Forward Transconductance
Total Gate Charge
Pre-Vth Gate-to-Source Charge
Post-Vth Gate-to-Source Charge
Gate-to-Drain Charge
Gate Charge Overdrive
Switch Charge (Q
gs2
+ Q
gd
)
Internal Gate Resistance
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Effective Output Capacitance
Internal Drain Inductance
Internal Source Inductance
Min.
150
–––
–––
3.0
–––
–––
–––
–––
–––
11
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Typ. Max. Units
–––
0.19
80
–––
-11
–––
–––
–––
–––
–––
13
3.3
0.8
3.9
5.0
4.1
2.5
7.0
6.6
13
3.1
810
100
15
97
4.5
7.5
–––
–––
95
4.9
–––
20
250
100
-100
–––
20
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
nH
–––
pF
V
GS
= 0V
V
DS
= 25V
ns
Ω
Conditions
V
GS
= 0V, I
D
= 250µA
V
GS
= 10V, I
D
= 5.2A
e
V
DS
= V
GS
, I
D
= 50µA
V
DS
= 150V, V
GS
= 0V
V
DS
= 150V, V
GS
= 0V, T
J
= 125°C
V
GS
= 20V
V
GS
= -20V
V
DS
= 50V, I
D
= 5.2A
V
DS
= 75V
V
mΩ
V
mV/°C
µA
nA
S
V/°C Reference to 25°C, I
D
= 1mA
nC
V
GS
= 10V
I
D
= 5.2A
See Fig. 6 and 19
V
DD
= 75V, V
GS
= 10V
I
D
= 5.2A
R
G
= 2.4Ω
e
ƒ = 1.0MHz,
Between lead,
6mm (0.25in.)
from package
See Fig.5
V
GS
= 0V, V
DS
= 0V to 120V
D
G
S
and center of die contact
Diode Characteristics
h
Parameter
I
S
@ T
C
= 25°C Continuous Source Current
I
SM
V
SD
t
rr
Q
rr
(Body Diode)
Pulsed Source Current
(Body Diode)
c
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Min.
–––
–––
–––
–––
–––
Typ. Max. Units
–––
–––
–––
57
140
8.7
A
34
1.3
86
210
V
ns
nC
Conditions
MOSFET symbol
showing the
integral reverse
p-n junction diode.
T
J
= 25°C, I
S
= 5.2A, V
GS
= 0V
e
T
J
= 25°C, I
F
= 5.2A
di/dt = 100A/µs
e
Notes:
Repetitive rating; pulse width limited by max. junction temperature.
Starting T
J
= 25°C, L = 5.8mH, R
G
= 25Ω, I
AS
= 5.2A.
Pulse width
≤
400µs; duty cycle
≤
2%.
R
θ
is measured at
T
J
of approximately 90°C.
Limited by Tjmax. See Figs. 14, 15, 17a, 17b for repetitive
avalanche information
Specifications refer to single MosFET.
2
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IRFI4019H-117P
100
TOP
VGS
15V
12V
10V
9.0V
8.0V
7.0V
6.0V
5.5V
100
TOP
VGS
15V
12V
10V
9.0V
8.0V
7.0V
6.0V
5.5V
ID, Drain-to-Source Current (A)
10
BOTTOM
ID, Drain-to-Source Current (A)
10
BOTTOM
1
5.5V
1
5.5V
0.1
≤
60µs PULSE WIDTH
Tj = 25°C
0.01
0.1
1
10
100
≤
60µs PULSE WIDTH
Tj = 150°C
0.1
0.1
1
10
100
VDS , Drain-to-Source Voltage (V)
VDS , Drain-to-Source Voltage (V)
Fig 1.
Typical Output Characteristics
100
Fig 2.
Typical Output Characteristics
2.5
RDS(on) , Drain-to-Source On Resistance
ID = 5.2A
2.0
ID, Drain-to-Source Current
(Α)
VGS = 10V
10
(Normalized)
TJ = 175°C
1.5
1
TJ = 25°C
VDS = 50V
1.0
0.5
≤
60µs PULSE WIDTH
0.1
4
5
6
7
8
0.0
-60 -40 -20
0
20
40
60
80 100 120 140 160
VGS, Gate-to-Source Voltage (V)
TJ, Junction Temperature (°C)
Fig 3.
Typical Transfer Characteristics
Fig 4.
Normalized On-Resistance vs. Temperature
20
VGS, Gate-to-Source Voltage (V)
100000
10000
VGS = 0V,
f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
ID= 5.2A
16
VDS = 120V
VDS= 75V
VDS= 30V
C, Capacitance (pF)
1000
Ciss
Coss
Crss
12
100
8
10
4
1
1
10
100
1000
0
0
5
10
15
20
QG Total Gate Charge (nC)
VDS , Drain-to-Source Voltage (V)
Fig 5.
Typical Capacitance vs.Drain-to-Source Voltage
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Fig 6.
Typical Gate Charge vs.Gate-to-Source Voltage
3
IRFI4019H-117P
100
100
ID, Drain-to-Source Current (A)
OPERATION IN THIS AREA
LIMITED BY R DS (on)
1msec
100µsec
ISD , Reverse Drain Current (A)
10
TJ = 150°C
10
DC
1
10msec
1
TJ = 25°C
VGS = 0V
0.1
0.0
0.5
1.0
1.5
Tc = 25°C
Tj = 150°C
Single Pulse
0.1
1
10
100
1000
VSD , Source-to-Drain Voltage (V)
VDS , Drain-toSource Voltage (V)
Fig 7.
Typical Source-Drain Diode Forward Voltage
10
5.0
Fig 8.
Maximum Safe Operating Area
8
VGS(th) Gate threshold Voltage (V)
ID , Drain Current (A)
4.0
6
ID = 50µA
4
3.0
2
0
25
50
75
100
125
150
2.0
-75
-50
-25
0
25
50
75
100
125
150
TJ , Junction Temperature (°C)
TJ , Temperature ( °C )
Fig 9.
Maximum Drain Current vs. Case Temperature
10
Fig 10.
Threshold Voltage vs. Temperature
D = 0.50
Thermal Response ( Z thJC )
1
0.20
0.10
0.05
0.02
0.01
R
1
R
1
τ
J
τ
1
τ
2
R
2
R
2
R
3
R
3
τ
C
τ
1
τ
2
τ
3
τ
3
τ
0.1
Ri (°C/W)
τ
J
τι
(sec)
Ci=
τi/Ri
Ci=
τi/Ri
1.508254 0.000814
2.154008 0.111589
3.237738 2.2891
0.01
SINGLE PULSE
( THERMAL RESPONSE )
0.001
1E-006
1E-005
0.0001
0.001
0.01
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.1
1
10
t1 , Rectangular Pulse Duration (sec)
Fig 11.
Maximum Effective Transient Thermal Impedance, Junction-to-Case
4
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IRFI4019H-117P
Ω
RDS (on), Drain-to -Source On Resistance ( )
EAS, Single Pulse Avalanche Energy (mJ)
0.5
350
ID = 5.2A
0.4
300
250
200
150
100
50
0
25
50
75
0.91A
1.1A
BOTTOM
5.2A
TOP
ID
0.3
0.2
TJ = 125°C
0.1
TJ = 25°C
0.0
4
5
6
7
8
9
10
100
125
150
VGS, Gate-to-Source Voltage (V)
Starting TJ, Junction Temperature (°C)
Fig 12.
On-Resistance Vs. Gate Voltage
Fig 13.
Maximum Avalanche Energy Vs. Drain Current
D.U.T
Driver Gate Drive
+
P.W.
Period
D=
P.W.
Period
V
GS
=10V
-
+
Circuit Layout Considerations
•
Low Stray Inductance
•
Ground Plane
•
Low Leakage Inductance
Current Transformer
***
D.U.T. I
SD
Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. V
DS
Waveform
Diode Recovery
dv/dt
-
-
+
R
G
*
•
•
•
•
dv/dt controlled by R
G
Driver same type as D.U.T.
I
SD
controlled by Duty Factor "D"
D.U.T. - Device Under Test
V
DD
V
DD
**
+
-
Re-Applied
Voltage
Inductor Curent
Body Diode
Forward Drop
Ripple
≤
5%
I
SD
*
Use P-Channel Driver for P-Channel Measurements
**
Reverse Polarity for P-Channel
***
V
GS
= 5V for Logic Level Devices
Fig 14.
Diode Reverse Recovery Test Circuit
for HEXFET
®
Power MOSFETs
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