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STT3414

Description
Super high dense cell design for low RDS(ON).
File Size117KB,7 Pages
ManufacturerSAMHOP
Websitehttp://www.samhop.com.tw
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STT3414 Overview

Super high dense cell design for low RDS(ON).

Gre
r
Pro
STT3414
Ver 1.0
S a mHop Microelectronics C orp.
N-Channel Logic Level Enhancement Mode Field Effect Transistor
PRODUCT SUMMARY
V
DSS
I
D
R
DS(ON)
(m
Ω
) Max
33
@
VGS=10V
30V
7A
42
@
VGS=4.5V
57
@
VGS=2.5V
FEATURES
Super high dense cell design for low R
DS(ON)
.
Rugged and reliable.
Surface Mount Package.
D
D
G
G
D
S
S
STT SERIES
SOT-223
ABSOLUTE MAXIMUM RATINGS (
T
A
=25
°
C unless otherwise noted
)
Symbol
V
DS
V
GS
I
D
I
DM
E
AS
P
D
T
J,
T
STG
Parameter
Drain-Source Voltage
Gate-Source Voltage
Drain Current-Continuous
-Pulsed
b
d
a
Limit
30
±12
T
A
=25°C
T
A
=70°C
7
5.6
28
9
T
A
=25°C
T
A
=70°C
3
1.9
-55 to 150
Units
V
V
A
A
A
mJ
W
W
°C
Single Pulse Avalanche Energy
Maximum Power Dissipation
a
Operating Junction and Storage
Temperature Range
THERMAL CHARACTERISTICS
R
JA
Thermal Resistance, Junction-to-Ambient
a
42
°C/W
Details are subject to change without notice.
Aug,23,2011
1
www.samhop.com.tw

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