P
RELIMINARY
P
RODUCT
S
PECIFICATION
1
Z86C02/E02/L02
C
OST
E
FFECTIVE
, 512-B
YTE
ROM
CMOS Z8
®
M
ICROCONTROLLERS
FEATURES
Device
Z86C02
Z86E02
Z86L02
ROM
(KB)
512
512
512
RAM* Speed Auto Permanent
(Bytes) (MHz) Latch
WDT
61
61
61
8
8
8
Optional Optional
Optional Optional
Optional Optional
s
1
ROM Mask/OTP Options:
–
Low-Noise (Z86C02/E02 only)
–
–
–
–
–
ROM Protect
Auto Latch
Permanent Watch-Dog Timer (WDT)
RC Oscillator (Z86C02/L02 Only)
32 KHz Operation (Z86C02/L02 Only)
Note:
*General-Purpose
s
s
18-Pin DIP and SOIC Packages
s
0
°
C to 70
°
C Standard Temperature
–40
°
C to 105
°
C Extended Temperature
(Z86C02/E02 only)
3.0V to 5.5V Operating Range (Z86C02)
4.5V to 5.5V Operating Range (Z86E02)
2.0V to 3.9V Operating Range (Z86L02)
14 Input / Output Lines
Five Vectored, Prioritized Interrupts from Five Different
Sources
Two On-Board Comparators
Software Enabled Watch-Dog Timer (WDT)
Programmable Interrupt Polarity
Two Standby Modes: STOP and HALT
Low-Voltage Protection
One Programmable 8-Bit Counter/Timer with a 6-Bit
Programmable Prescaler
Power-On Reset (POR) Timer
On-Chip Oscillator that Accepts RC, Crystal, Ceramic
Resonator, LC, or External Clock Drive (C02/L02 only)
On-Chip Oscillator that Accepts RC or External Clock
Drive (Z86E02 SL1903 only)
On-Chip Oscillator that Accepts Crystal, Ceramic
Resonator, LC, or External Clock Drive (Z86E02 only)
Clock-Free WDT Reset
Low-Power Consumption (50mw)
Fast Instruction Pointer (1.5
µ
s @ 8 MHz)
Fourteen Digital Inputs at CMOS Levels;
Schmitt-Triggered
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
GENERAL DESCRIPTION
Zilog's Z86C02/E02/L02 microcontrollers (MCUs) are
members of the Z8
®
single-chip MCU family, which offer
easy software/hardware system expansion.
For applications demanding powerful I/O capabilities, the
MCU's dedicated input and output lines are grouped into
three ports, and are configurable under software control to
provide timing, status signals, or parallel I/O.
One on-chip counter/timer, with a large number of user-se-
lectable modes, off-load the system of administering real-
time tasks such as counting/timing and I/O data communi-
DS96DZ80301
PRELIMINARY
1
Z86C02/E02/L02
Cost Effective, 512-Byte ROM CMOS Z8
®
Microcontrollers
Zilog
GENERAL DESCRIPTION
(Continued)
cations. Additionally, two on-board comparators process
analog signals with a common reference voltage (Figure
1).
Note:
All Signals with a preceding front slash, "/", are ac-
tive Low, e.g.: B//W (WORD is active Low); /B/W (BYTE is
active Low, only).
Input
Vcc
GND
Power connections follow conventional descriptions be-
low:
Connection
Power
Ground
XTAL
Circuit
V
CC
GND
Device
V
DD
V
SS
Port 3
Machine
Timing & Inst.
Control
Counter/
Timer
ALU
Interrupt
Control
FLAG
Program
Memory
Two Analog
Comparators
Register
Pointer
General-Purpose
Register File
Program
Counter
Port 2
Port 0
I/O
(Bit Programmable)
I/O
Figure 1. Z86C02/E02/L02 Functional Block Diagram
2
PRELIMINARY
DS96DZ80301
Z86C02/E02/L02
Cost Effective, 512-Byte ROM CMOS Z8
®
Microcontrollers
Zilog
GENERAL DESCRIPTION
(Continued)
D7-D0
Z8 MCU
A10-A0
Address
Counter
A10-A0
3 Bits
PGM
Mode Logic
Option Bits
D7-D0
Address MUX
A10-A0
Data MUX
Z8 PORT2
/OE
P31
EPROM
D7-D0
Clear Clock
P00 P01
EPM /CE /PGM
P32 XT1 P02
VPP
P33
Figure 2. EPROM Programming Mode Block Diagram
PIN DESCRIPTIONS
Table 1. 18-Pin Standard Mode Identification
P24
P25
P26
P27
Vcc
XTAL2
XTAL1
P31
P32
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
P23
P22
P21
P20
GND
P02
P01
P00
P33
Pin #
1-4
5
6
7
8
9
10
11-13
14
15-18
Symbol
Function
Direction
In/Output
Output
Input
Input
Input
Input
In/Output
In/Output
P24-P27 Port 2, Pins 4, 5, 6, 7
Power Supply
V
CC
Crystal Oscillator
Clock
XTAL1
Crystal Oscillator
Clock
P31
Port 3, Pin 1, AN1
P32
Port 3, Pin 2, AN2
P33
Port 3, Pin 3, REF
P00-P02
Port 0, Pins 0, 1, 2
GND
Ground
P20-P23 Port 2, Pins 0, 1, 2, 3
XTAL2
Standard Mode
Figure 3. 18-Pin Standard Mode Configuration
3
PRELIMINARY
DS96DZ80301
Zilog
D4
D5
D6
D7
Vcc
N/C
/CE
/OE
EPM
D3
D2
D1
D0
GND
/PGM
CLOCK
CLEAR
VPP
Cost Effective, 512-Byte ROM CMOS
Z8
®
Z86C02/E02/L02
Microcontrollers
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
P24
P25
P26
P27
VCC
XTAL2
XTAL1
P31
P32
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
P23
P22
P21
P20
GND
P02
P01
P00
P33
1
EPROM Mode
Figure 4. 18-Pin EPROM Mode Configuration
Table 2. 18-Pin EPROM Mode Identification
Pin #
1-4
5
6
7
8
9
10
11
12
13
14
15-18
Symbol
D4-D7
Vcc
NC
/CE
/OE
EPM
VPP
Clear
Clock
/PGM
GND
D0-D3
Function
Data 4, 5, 6, 7
Power Supply
No Connection
Chip Enable
Output Enable
EPROM Program
Mode
Program Voltage
Clear Clock
Address
Program Mode
Ground
Data 0, 1, 2, 3
Direction
In/Output
Pin #
1-4
Input
Input
Input
Input
Input
Input
Input
In/Output
5
6
7
8
9
10
11-13
14
15-18
Figure 5. 18-Pin SOIC Configuration
Table 3. 18-Pin SOIC Pin Identification
Standard Mode
Symbol
P24-P27
Vcc
XTAL2
XTAL1
P31
P32
P33
P00-P02
GND
P20-P23
Function
Port 2, Pins
4,5,6,7
Power Supply
Crystal Osc. Clock
Crystal Osc. Clock
Port 3, Pin 1, AN1
Port 3, Pin 2, AN2
Port 3, Pin 3, REF
Port 0, Pins 0,1,2
Ground
Port 2, Pins
0,1,2,3
Direction
In/Output
Output
Input
Input
Input
Input
In/Output
In/Output
DS96DZ80301
PRELIMINARY
4
Zilog
Cost Effective, 512-Byte ROM CMOS
Z8
®
Z86C02/E02/L02
Microcontrollers
ABSOLUTE MAXIMUM RATINGS
Parameter
Ambient Temperature under Bias
Storage Temperature
Voltage on any Pin with Respect to V
SS
[Note 1]
Voltage on V
DD
Pin with Respect to V
SS
Voltage on Pin 7 with Respect to V
SS
[Note 2] (Z86C02/L02)
Voltage on Pin 7,8,9,10 with Respect to V
SS
[Note 2] (Z86E02)
Total Power Dissipation
Maximum Allowed Current out of V
SS
Maximum Allowed Current into V
DD
Maximum Allowed Current into an Input Pin [Note 3]
Maximum Allowed Current into an Open-Drain Pin [Note 4]
Maximum Allowed Output Current Sinked by Any I/O Pin
Maximum Allowed Output Current Sourced by Any I/O Pin
Maximum Allowed Output Current Sinked by Port 2, Port 0
Maximum Allowed Output Current Sourced by Port 2, Port 0
Notes:
Stresses greater than those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. This is a stress rating only; functional operation of
the device at any condition above those indicated in the
operational sections of these specifications is not implied.
Exposure to absolute maximum rating conditions for an
extended period may affect device reliability.
Total power dissipation should not exceed 462 mW for the
package. Power dissipation is calculated as follows:
Total Power dissipation = V
DD
x [I
DD
– (sum of I
OH
)] + sum of [(V
DD
– V
OH
) x I
OH
] + sum of (V
0L
x I
0L
)
Min
–40
–65
–0.7
–0.3
–0.7
–0.7
Max
+105
+150
+12
+7
V
DD
+1
V
DD
+1
462
300
270
+600
+600
20
20
80
80
Units
C
C
V
V
V
V
mW
mA
mA
µA
µA
mA
mA
mA
mA
1
–600
–600
1. This applies to all pins except where otherwise noted.
2. Maximum current into pin must be
±
600
µ
A.
There is no input protection diode from pin to V
DD
.
3. This excludes Pin 6 and Pin 7.
4. Device pin is not at an output Low state.
STANDARD TEST CONDITIONS
The characteristics listed below apply for standard test
conditions as noted. All voltages are referenced to
Ground. Positive current flows into the referenced pin (Fig-
ure 6).
From Output
Under Test
150 pF
Figure 6. Test Load Diagram
CAPACITANCE
T
A
= 25
°
C, V
CC
= GND = 0V, f = 1.0 MHz, unmeasured pins returned to GND.
Parameter
Input capacitance
Output capacitance
I/O capacitance
DS96DZ80301
Min
0
0
0
Max
15 pF
20 pF
25 pF
PRELIMINARY
5
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