Application Specific Standard Clock (ASSC) for HD Video
FEATURES
Advanced low noise PLL design
Very low Jitter and Phase Noise (< 50ps Pk-Pk typical)
Complementary LVCMOS outputs to drive LVPECL and
LVDS inputs.
Output Frequency (Selectable using FSEL):
o
PL611-31A/B 148.50MHz/148.35164MHz
o
PL611-31C/D 74.25MHz/74.17582MHz
Input Frequency:
o
PL611-31A/C
27MHz Reference Clock
o
PL611-31B/D
27MHz Fundamental Crystal
Accepts <1.0V reference signal input voltage
Single 2.5V ~ 3.3V ± 10% power supply
Operating temperature range from -40C to 85C
Available in 8-pin MSOP/SOP and 6-pin SOT23
GREEN/RoHS compliant packages.
PIN CONFIGURATION
XIN/FIN
GND
CLK0
CLK1
1
2
3
4
8
7
6
5
XOUT
FSEL
DNC
VDD
(M)SOP-8L
PL611-31X
CLK1
GND
FIN
1
2
3
6
5
4
CLK0
VDD
FSEL
SOT23-6L
PL611-31A/C
DESCRIPTION
The PL611-31A/B/C/D are Application Specific Standard Clocks (ASSC) and members of PhaseLink’s PicoPLL
TM
Programmable product family. Designed to fit in a small 8-pin MSOP, 8-pin SOP or 6-pin SOT23 (-31A&C only)
package for high performance applications, the PL611-31A/B/C/D provide very low jitter and power consumption
while offering 2 selectable clock outputs using the Frequency Switching (FSEL) feature. The complementary
LVCMOS outputs can be used to drive LVCMOS, LVPECL or LVDS inputs. The PL611-31A/B/C/D are excellent
choices for HD Video designs that need to support both US and European standards. For applications requiring
alternate configurations to the ones shown, please refer to the PL611 programmable products on our website.
PRODUCT SELECTOR TABLE
Part Number
PL611-31A
PL611-31B
PL611-31C
PL611-31D
Input
27MHz
Reference Clock
27MHz Crystal
27MHz
Reference Clock
27MHz Crystal
FSEL State
1
0
1
0
1
0
1
0
CLK0/CLK1
Output Frequency (MHz)
148.50
148.35164
148.50
148.35164
74.25
74.17582
74.25
74.17582
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 9/27/07 Page 1
(Preliminary)
Application Specific Standard Clock (ASSC) for HD Video
BLOCK DIAGRAM
XIN / FIN
XOUT
Xtal
Osc
CLK0
PLL
CLK1
FSEL
PIN DESCRIPTION
Name
XIN/FIN
GND
CLK0
CLK1
VDD
DNC
FSEL
XOUT
Package Pin #
(M)SOP-8L
1
2
3
4
5
6
7
8
SOT23-6L
3
2
6
1
5
-
4
-
Type
I
P
O
O
P
-
B
O
Description
27MHz fundamental crystal or reference clock input.
FIN only for SOT23-6L package.
GND connection.
LVCMOS clock output.
Complementary LVCMOS clock output.
VDD connection (2.25~3.63V).
Do no connect.
Frequency Selection (FSEL) input pin. This pin has an
internal 60KΩ pull up resistor. See the PRODUCT
SELECTOR TABLE on page 1 for available options.
Crystal output pin. Do Not Connect when using
reference clock input on pin 1.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 9/27/07 Page 2
(Preliminary)
Application Specific Standard Clock (ASSC) for HD Video
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETERS
Supply Voltage Range
Input Voltage Range
Output Voltage Range
Data Retention @ 85º C
Soldering Temperature (Green Package)
Storage Temperature
Ambient Operating Temperature*
T
S
-65
-40
SYMBOL
V
DD
V
I
V
O
MIN.
-0.5
-0.5
-0.5
10
260
150
+85
MAX.
4.6
V
DD
+0.5
V
DD
+0.5
UNITS
V
V
V
Years
C
C
C
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device
and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above
the operational limits noted in this specification is not implied. *Operating temperature is guaranteed by design. Parts are tested to commercial grade only.
AC SPECIFICATIONS
PARAMETERS
Crystal Input Frequency
Input (FIN) Frequency
Input (FIN) Signal Amplitude
Settling Time
VDD Sensitivity
Output Rise Time
Output Fall Time
Duty Cycle
Max. output skew between clocks
Period Jitter, peak-to-peak
(10,000 samples measured)
At power-up (V
DD
< 2.25V)
Frequency vs. V
DD
+/-10%
15pF Load, 10/90%V
DD
15pF Load, 90/10%V
DD
At V
DD
/2
Equal loading (15 pF)
With capacitive decoupling between V
DD
and GND.
45
45
-2
1.0
1.0
50
0.9
CONDITIONS
Fundamental Crystal
MIN.
TYP.
27
27
V
DD
10
2
1.5
1.5
55
200
MAX.
UNITS
MHz
MHz
Vpp
ms
ppm
ns
ns
%
ps
ps
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 9/27/07 Page 3
(Preliminary)
Application Specific Standard Clock (ASSC) for HD Video
DC SPECIFICATIONS
PARAMETERS
SYMBOL
CONDITIONS
PL611-31A, 3.3V, No Load
Supply Current,
Dynamic
I
DD
PL611-31B, 3.3V, No Load
PL611-31C, 3.3V, No Load
PL611-31D, 3.3V, No Load
Operating Voltage
Output Low Voltage
Output High Voltage
Output Current
V
DD
V
OL
V
OH
I
OHD
I
OL
= +4mA
I
OH
= -4mA
V
OL
= 0.4V, V
OH
= 2.4V
V
DD
– 0.4
24
2.25
3.63
0.4
V
V
V
mA
20
mA
MIN.
TYP.
MAX.
UNITS
CRYSTAL SPECIFICATIONS (PL611-31B/D Only)
PARAMETERS
Fundamental Crystal Resonator Frequency
Crystal Loading Rating
Maximum Sustainable Drive Level
Operating Drive Level
Crystal Shunt Capacitance
Effective Series Resistance
C0
R
S
100
6
30
SYMBOL
F
XIN
C
L (xtal)
MIN.
TYP.
27
18
MAX.
UNITS
MHz
pF
500
W
W
pF
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 9/27/07 Page 4
(Preliminary)
Application Specific Standard Clock (ASSC) for HD Video
TERMINATION FOR LVPECL AND LVDS INPUTS
Figure 1 below describes how to terminate the complementary LVCMOS outputs of PhaseLink’s PL611-31A/B/C/D
ASSC clock for use with LVPECL or LVDS inputs.
+3.3V
LVCMOS Output
R1
50? line
R2
Input
R3
Complementary
LVCMOS Output
R1
50? line
R3
Complementary
Input
LVPECL LVDS
2.35V 1.40V
1.59V 1.10V
3.3V
0V
Component selection
For LVPECL input For LVDS input
R1 = 130?
R2 = 82?
R3 = 130?
R1 = 360?
R2 = 82?
R3 = 130?
R2
+3.3V
Notes:
Place R1 as close to the LVCMOS outputs as
possible.
Place R2 and R3 as close to the LVPECL/LVDS
inputs as possible.
Figure 1
The above layout allows the PL611-31 to drive either LVPECL or LVDS inputs by simply changing the value of R1.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
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