1. FEATURES .............................................................................................................................................................. 4
2. GENERAL DESCRIPTION ..................................................................................................................................... 6
6. DATA PROTECTION................................................................................................................................................ 9
Table 2. Protected Area Sizes ...................................................................................................................10
4 x I/O Read Mode (4READ) ................................................................................................................... 49
Fast Double Transfer Rate Read (FASTDTRD) ....................................................................................... 51
2 x I/O Double Transfer Rate Read Mode (2DTRD) ................................................................................ 52
4 x I/O Double Transfer Rate Read Mode (4DTRD) ................................................................................ 53
Preamble Bit ........................................................................................................................................... 55
4 Byte Address Command Set ................................................................................................................. 60
Fast Boot ................................................................................................................................................. 74
9-42. Program Suspend .................................................................................................................................... 98
11. POWER-ON STATE ........................................................................................................................................... 109
14. ERASE AND PROGRAMMING PERFORMANCE ............................................................................................ 118
15. DATA RETENTION ............................................................................................................................................ 118
17. ORDERING INFORMATION .............................................................................................................................. 119
18. PART NAME DESCRIPTION ............................................................................................................................. 120
19. PACKAGE INFORMATION ................................................................................................................................ 121
20. REVISION HISTORY ......................................................................................................................................... 123
P/N: PM2018
9-25.
9-26.
9-27.
9-28.
9-29.
9-30.
9-31.
9-32.
9-33.
9-34.
9-35.
9-36.
9-37.
3
REV. 1.0, OCT. 01, 2014
MX66L1G45G
3V 1G-BIT [x 1/x 2/x 4] CMOS MXSMIO
(SERIAL MULTI I/O)
FLASH MEMORY
1. FEATURES
GENERAL
•
Supports Serial Peripheral Interface -- Mode 0 and Mode 3
• Single Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program operations
• Protocol Support
- Single I/O, Dual I/O and Quad I/O
• Latch-up protected to 100mA from -1V to Vcc +1V
• Low Vcc write inhibit is from 2.3V to 2.5V
• Fast read for SPI mode
- Support clock frequency up to 166MHz
- Support Fast Read, 2READ, DREAD, 4READ, QREAD instructions
- Support DTR (Double Transfer Rate) Mode
- Configurable dummy cycle number for fast read operation
• Quad Peripheral Interface (QPI) available
• Equal Sectors with 4K byte each, or Equal Blocks with 32K byte each or Equal Blocks with 64K byte each
- Any Block can be erased individually
• Programming :
- 256byte page buffer
- Quad Input/Output page program(4PP) to enhance program performance
• Typical 100,000 erase/program cycles
• 20 years data retention
SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
• Advanced Security Features
- Block lock protection
The BP0-BP3 and T/B status bits define the size of the area to be protected against program and erase
instructions
- Advanced sector protection function (Solid and Password Protect)
• Additional 4K bit security OTP
-
Features unique identifier
-
factory locked identifiable, and customer lockable
•
Command Reset
•
Program/Erase Suspend and Resume operation
•
Electronic Identification
-
JEDEC 1-byte manufacturer ID and 2-byte device ID
- RES command for 1-byte Device ID
- REMS command for 1-byte manufacturer ID and 1-byte device ID
•
Support Serial Flash Discoverable Parameters (SFDP) mode
P/N: PM2018
4
REV. 1.0, OCT. 01, 2014
MX66L1G45G
HARDWARE FEATURES
•
SCLK Input
- Serial clock input
• SI/SIO0
- Serial Data Input or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode
• SO/SIO1
- Serial Data Output or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode
• WP#/SIO2
- Hardware write protection or serial data Input/Output for 4 x I/O read mode
• RESET#/SIO3
- Hardware Reset pin or Serial input & Output for 4 x I/O read mode
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