Datasheet
R1QEA4436RBG, R1QEA4418RBG
144-Mbit DDR™II+ SRAM 2-word Burst
Architecture ( 2.5 Cycle Read latency ) with ODT
Description
The R1QEA4436RBG is a 4,194,304-word by 36-bit and the R1QEA4418RBG is a 8,388,608-word by 18-bit
synchronous double data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor
memory cell. It integrates unique synchronous peripheral circuitry and a burst counter. All input registers are
controlled by an input clock pair (K and /K) and are latched on the positive edge of K and /K. These products are
suitable for applications which require synchronous operation, high speed, low voltage, high density and wide bit
configuration. These products are packaged in 165-pin plastic FBGA package.
R10DS0142EJ0200
Rev.2.00
Apr 01, 2014
Features
Power Supply
1.8 V for core (V
DD
), 1.4 V to VDD for I/O (V
DDQ
)
Clock
Fast clock cycle time for high bandwidth
Two input clocks (K and /K) for precise DDR timing at clock rising edges only
Two output echo clocks (CQ and /CQ) simplify data capture in high-speed systems
Clock-stop capability with
μs
restart
I/O
Common data input/output bus
Pipelined double data rate operation
HSTL I/O
User programmable output impedance
PLL circuitry for wide output data valid window and future frequency scaling
Data valid pin (QVLD) to indicate valid data on the output
Function
Two-tick burst for low DDR transaction size
Internally self-timed write control
Simple control logic for easy depth expansion
JTAG 1149.1 compatible test access port
Package
165 FBGA package (15 x 17 x 1.4 mm)
R10DS0142EJ0200 Rev.2.00
Aug 01, 2014
Page 1 of 30
R1QEA4436RBG, R1QEA4418RBG
Datasheet
Part Number Definition
Column No.
Example
0
1
2
3
4
5
6
7
8
9
10
11
-
12
13
14
15
16
R
1
Q
E
A
4
4
3
6
R
B
G
-
1
8
I
B
0
The above part number is just example for 144M DDRII+ B2 x36 550MHz, 15x17mm PKG, Pb-free part.
No.
0-1
2-3
-
R1
Q2
Q3
Q4
Q5
Q6
QA
QB
QC
QD
QE
QF
QG
QH
QJ
QK
QL
QM
QN
QP
-
Comments
Renesas Memory Prefix
[*1]
[*2]
(L15)
QDR II B2
QDR II B4
(L15)
DDR II B2
(L15)
DDR II B4
(L15)
[*3]
(L15)
DDR II B2 SIO
[*2]
QDR II+ B4 L25
DDR II+ B2 L25
DDR II+ B4 L25
[*4]
QDR II+ B4 L25 w/ODT
DDR II+ B2 L25 w/ODT
DDR II+ B4 L25 w/ODT
QDR II+ B4 L20
DDR II+ B2 L20
DDR II+ B4 L20
QDR II+ B4 L20 w/ODT
DDR II+ B2 L20 w/ODT
DDR II+ B4 L20 w/ODT
QDR II+ B2 L20
QDR II+ B2 L20 w/ODT
-
No.
4
5-6
7-8
9
10-11
-
A
36
72
44
88
09
18
36
R
A
B
C
D
E
F
BG
BB
Comments
Vdd = 1.8 V
Density = 36Mb
Density = 72Mb
Density = 144Mb
Density = 288Mb
Data width = 9bit
Data width = 18bit
Data width = 36bit
1st Generation
2nd Generation
3rd Generation
4th Generation
5th Generation
6th Generation
7th Generation
PKG= BGA 15x17 mm
PKG= BGA 13x15 mm
No.
12-13
-
60
50
40
36
33
30
27
25
22
20
19
18
R
14
I
15
-
-
-
16
A
B
T
S
0 to 9,
A to Z Renesas internal use
or None
Comments
Frequency = 167MHz
Frequency = 200MHz
Frequency = 250MHz
Frequency = 275MHz
Frequency = 300MHz
Frequency = 333MHz
Frequency = 375MHz
Frequency = 400MHz
Frequency = 450MHz
Frequency = 500MHz
Frequency = 533MHz
Frequency = 550MHz
Commercial temp.
Ta range = 0℃ to 70℃
Industrial temp.
Ta range = -40℃ to 85℃
Pb-and Tray
Pb-free and Tray
Pb-and Tape&Reel
Pb-free and Tape&Reel
Note1:
[*1]
[*2]
[*3]
[*4]
B=Burst length (B2: Burst length=2, B4: Burst length=4)
L=Read Latency (L15: Read Latency = 1.5 cycle, L20: 2.0 cycle, L25: 2.5 cycle)
SIO=Separate I/O
ODT=On die termination
Note2:
Package Marking Name
Pb-parts: Marking Name = Part Number(0-14)
Pb-free parts: Marking Name = Part Number(0-14) + "PB-F"
(Example) R1QAA4436RBG-20R
Pb-F
----- Pb-parts
(Example)
R1QAA4436RBG-20R PB-F ----- Pb-free parts
Pb-free: RoHS Compliance Level = 5/6
Pb-free: RoHS Compliance Level = 6/6
R1Q*A series support both "Commercial" and "Industrial" temperatures
by "Industrial" temperature parts.
Note3:
Note4:
R10DS0142EJ0200 Rev.2.00
Aug 01, 2014
Page 2 of 30
Microchip MCU
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