EN27LN51208
EN27LN51208
512 Megabit (64 M x 8) SLC, 3.3 V NAND Flash Memory
1. Features
•
Voltage Supply: 3.3V (2.7V ~ 3.6V )
•
Organization
x 8:
- Memory Cell Array :
(64M + 2M) x 8bit
- Data Register : (2K + 64) x 8bit
•
Automatic Program and Erase
x 8:
- Page Program : (2K + 64) Byte
- Block Erase : (128K + 4K) Byte
•
Page Read Operation
- Page Size : (2K + 64) Byte (x 8)
- Random Read : 25µs (Max.)
- Serial Access : 25ns (Min.)
•
Memory Cell: 1bit/Memory Cell
•
Fast Write Cycle Time
- Page Program Time : 300µs (Typ.)
- Block Erase Time : 3ms (Typ.)
•
Command/Address/Data Multiplexed I/O Port
•
Hardware Data Protection
- Program/Erase Lockout During Power
Transitions
•
Reliable CMOS Floating-Gate Technology
- ECC Requirement: x 8 - 4bit/512 Byte
- Endurance: 100K Program/Erase cycles
- Data Retention: 10 years
•
Command Register Operation
•
Automatic Page 0 Read at Power-Up Option
- Boot from NAND support
- Automatic Memory Download
•
NOP: 4 cycles
•
Cache Program Operation for High Performance
Program
•
Cache Read Operation
•
Copy-Back Operation
•
EOD mode
•
OTP Operation
•
Bad-Block-Protect
•
Commercial temperature Range
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. A, Issue Date: 2013/09/30
EN27LN51208
2. General Description
The Eon EN27LN51208 is a 64Mx8bit with spare 2Mx8bit capacity. The device is offered in 3.3V Vcc
Power Supply. Its NAND cell provides the most cost-effective solution for the solid state mass storage
market. The memory is divided into blocks that can be erased independently so it is possible to preserve
valid data while old data is erased.
The device contains 512 blocks, composed by 64 pages consisting in two NAND structures of 32 series
connected Flash cells. A program operation allows to write the 2,112-Byte page in typical 250us and an
erase operation can be performed in typical 2ms on a 128K-Byte for X 8 device block.
Data in the page mode can be read out at 25ns cycle time per Word. The I/O pins serve as the ports for
address and command inputs as well as data input/output. The copy back function allows the
optimization of defective blocks management: when a page program operation fails the data can be
directly programmed in another page inside the same array section without the time consuming serial
data insertion phase. The cache program feature allows the data insertion in the cache register while
the data register is copied into the Flash array. This pipelined program operation improves the program
throughput when long files are written inside the memory. A cache read feature is also implemented.
This feature allows to dramatically improving the read throughput when consecutive pages have to be
streamed out. This device includes extra feature: Automatic Read at Power Up.
3. Package
Pin Configuration
Figure 1. Pin-Out Diagram of x 8 Device
(TOP VIEW)
(TSOPI 48L, 12mm X 20mm Body, 0.5mm Pin Pitch)
NC
NC
NC
NC
NC
NC
R/B#
RE#
CE#
NC
NC
Vcc
Vss
NC
NC
CLE
ALE
WE#
WP#
NC
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
NC
NC
NC
NC
I/O7
I/O6
I/O5
I/O4
NC
NC
NC
Vcc
Vss
NC
NC
NC
I/O3
I/O2
I/O1
I/O0
NC
NC
NC
NC
Standard
TSOP I
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. A, Issue Date: 2013/09/30
EN27LN51208
Package Dimension
Figure 2. 48L TSOPI 12mm x 20mm package outline
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. A, Issue Date: 2013/09/30
EN27LN51208
4. Pin Description
Function
The I/O pins are used to input command, address and data, and
I/O0 – I/O7 (x 8) Data Inputs/Outputs to output data during read operations. The I/O pins float to Hi-Z
when the chip is deselected or when the outputs are disabled.
The CLE input controls the activating path for commands sent to
Command Latch
the command register. When active high, commands are latched
CLE
Enable
into the command register through the I/O ports on the rising edge
of the WE# signal.
The ALE input controls the activating path for addresses sent to
the internal address registers. Addresses are latched into the
Address Latch
ALE
address register through the I/O ports on the rising edge of WE#
Enable
with ALE high.
The CE# input is the device selection control. When the device is
in the Busy state, CE# high is ignored, and the device does not
CE#
Chip Enable
return to standby mode in program or erase operation. Regarding
CE# control during read operation, refer to ’Page read’ section of
Device operation.
The RE# input is the serial data-out control, and when it is active
low, it drives the data onto the I/O bus. Data is valid t
REA
after the
RE#
Read Enable
falling edge of RE# which also increments the internal column
address counter by one.
The WE# input controls writes to the I/O port. Commands,
WE#
Write Enable
address and data are latched on the rising edge of the WE# pulse.
The WP# pin provides inadvertent program/erase protection
WP#
Write Protect
during power transitions. The internal high voltage generator is
reset when the WP# pin is active low.
The R/B# output indicates the status of the device operation.
When low, it indicates that a program, erase or random read
Ready/Busy Output
operation is in process and returns to high state upon completion.
R/B#
It is an open drain output and does not float to Hi-Z condition
when the chip is deselected or when outputs are disabled.
V
CC
V
SS
NC
Power Supply
Ground
No Connection
Lead is not internally connected.
V
CC
is the power supply for device.
Symbol
Pin Name
Note:
Connect all V
CC
and V
SS
pins of each device to common power supply outputs. Do not leave V
CC
or V
SS
disconnected.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. A, Issue Date: 2013/09/30
EN27LN51208
5. Block Diagram
Figure 3. Functional Block Diagram (x8)
Figure 4. Array Organization (x8)
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. A, Issue Date: 2013/09/30
京公网安备 11010802033920号
EEWORLD
