EN29PL064 datasheet, PDF - EEWORLD Datasheet

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EN29PL064: Description64 Mbit (4 M x 16-Bit) CMOS 3.0 Volt- only; File Size771KB，57 Pages; ManufacturerEon; Websitehttp://www.essi.com.tw/

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EN29PL064 Overview

64 Mbit (4 M x 16-Bit) CMOS 3.0 Volt- only

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EN29PL064

Purpose

Eon Silicon Solution Inc. (hereinafter called “Eon”) is going to provide its products’ top marking on

ICs with < cFeon > from January 1st, 2009, and without any change of the part number and the

compositions of the ICs. Eon is still keeping the promise of quality for all the products with the

same as that of Eon delivered before. Please be advised with the change and appreciate your

kindly cooperation and fully support Eon’s product family.

Eon products’ New Top Marking

cFeon Top Marking Example:

cFeon

Part Number: XXXX-XXX

Lot Number: XXXXX

Date Code: XXXXX

Continuity of Specifications

There is no change to this data sheet as a result of offering the device as an Eon product. Any

changes that have been made are the result of normal data sheet improvement and are noted in

the document revision summary, where supported. Future routine revisions will occur when

appropriate, and changes will be noted in a revision summary.

Continuity of Ordering Part Numbers

Eon continues to support existing part numbers beginning with “Eon” and “cFeon” top marking. To

order these products, during the transition please specify “Eon top marking” or “cFeon top marking”

on your purchasing orders.

For More Information

Please contact your local sales office for additional information about Eon memory solutions.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

Rev. K, Issue Date: 2010/12/27

EN29PL064

1. Simultaneous Read/Write Operation with Zero Latency

The Simultaneous Read/Write architecture provides

simultaneous operation

by dividing the memory

space into 4 banks, which can be considered to be four separate memory arrays as far as certain

operations are concerned. The device can improve overall system performance by allowing a host

system to program or erase in one bank, then immediately and simultaneously read from another bank

with zero latency (with two simultaneous operations operating at any one time). This releases the

system from waiting for the completion of a program or erase operation, greatly improving system

performance.

The device can be organized in both top and bottom sector configurations. The banks are organized

as follows:

Bank

Sectors

8 Mbit (4 Kw x 8 and 32 Kw x 15)

24 Mbit (32 Kw x 48)

8 Mbit (4 Kw x 8 and 32 Kw x 15)

1.1 Page Mode Features

The page size is 4 words. After initial page access is accomplished, the page mode operation provides

fast read access speed of random locations within that page.

1.2 Standard Flash Memory Features

The device requires a

single 3.0 volt power supply

(2.7 V to 3.6 V) for both read and write functions.

Internally generated and regulated voltages are provided for the program and erase operations.

The device is entirely command set compatible with the

JEDEC 42.4 single-power-supply Flash

standard.

Commands are written to the command register using standard microprocessor write timing.

circuitry. Write cycles also internally latch addresses and data needed for the programming and erase

operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.

Device programming occurs by executing the program command sequence. The Accelerated Program

mode facilitates faster programming times by requiring only two write cycles to program data instead of

four. Device erasure occurs by executing the erase command sequence.

The host system can detect whether a program or erase operation is complete by reading the DQ7

(Data# Polling) and DQ6 (toggle)

status bits.

After a program or erase cycle has been completed, the

device is ready to read array data or accept another command.

The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting

the data contents of other sectors. The device is fully erased when shipped from the factory.

Hardware data protection

measures include a low V

detector that automatically inhibits write

operations during power transitions. The hardware sector protection feature disables both program and

erase operations in any combination of sectors of memory. This can be achieved in-system or via

programming equipment.

The Erase Suspend/Erase Resume

feature enables the user to put erase on hold for any period of

time to read data from, or program data to, any sector that is not selected for erasure. True background

erase can thus be achieved. If a read is needed from the Secured Silicon Sector area (One Time

Program area) after an erase suspend, then the user must use the proper command sequence to enter

and exit this region.

The

Program Suspend/Program Resume

feature enables the user to hold the program operation to

read data from any sector that is not selected for programming. If a read is needed from the Secured

Silicon Sector area, Persistent Protection area, or the CFI area, after a program suspend, then the user

must use the proper command sequence to enter and exit this region.

The device offers two power-saving features. When addresses have been stable for a specified amount

of time, the device enters the

automatic sleep mode.

The system can also place the device into the

standby mode. Power consumption is greatly reduced in both these modes.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

www.eonssi.com

Rev. K, Issue Date: 2010/12/27

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