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ADF4153_15: DescriptionFractional-N Frequency Synthesizer; File Size352KB，24 Pages; ManufacturerADI; Websitehttps://www.analog.com

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ADF4153_15 Overview

Fractional-N Frequency Synthesizer

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Data Sheet

FEATURES

Fractional-N Frequency Synthesizer

ADF4153

GENERAL DESCRIPTION

The ADF4153 is a fractional-N frequency synthesizer

that implements local oscillators in the upconversion

and downconversion sections of wireless receivers and

transmitters. It consists of a low noise digital phase

frequency detector (PFD), a precision charge pump, and

a programmable reference divider. There is a Σ-Δ based

fractional interpolator to allow programmable fractional-N

division. The INT, FRAC, and MOD registers define an

overall N divider (N = (INT + (FRAC/MOD))). In addition,

the 4-bit reference counter (R counter) allows selectable

REFIN frequencies at the PFD input. A complete phase-

locked loop (PLL) can be implemented if the synthesizer is

used with an external loop filter and a voltage controlled

oscillator (VCO).

A simple 3-wire interface controls all on-chip registers.

The device operates with a power supply ranging from

2.7 V to 3.3 V and can be powered down when not in use.

RF bandwidth to 4 GHz

2.7 V to 3.3 V power supply

Separate V

allows extended tuning voltage

Y version available: −40°C to +125°C

Programmable fractional modulus

Programmable charge pump currents

3-wire serial interface

Analog and digital lock detect

Power-down mode

Pin-compatible with ADF4110/ADF4111/ADF4112/ADF4113

and ADF4106

Consistent RF output phase

Loop filter design possible with ADIsimPLL

Qualified for automotive applications

APPLICATIONS

CATV equipment

Base stations for mobile radio (GSM, PCS, DCS, WiMAX,

SuperCell 3G, CDMA, W-CDMA)

Wireless handsets (GSM, PCS, DCS, CDMA, W-CDMA)

Wireless LANs, PMR

Communications test equipment

FUNCTIONAL BLOCK DIAGRAM

SDV

SET

ADF4153

REF

×2

DOUBLER

4-BIT

R COUNTER

DGND

LOCK

DETECT

MUXOUT

OUTPUT

MUX

DIV

N-COUNTER

THIRD ORDER

FRACTIONAL

INTERPOLATOR

CLK

DATA

24-BIT

DATA

FRACTION

REG

MODULUS

REG

INTEGER

REG

CURRENT

SETTING

RFCP3 RFCP2 RFCP1

PHASE

FREQUENCY

DETECTOR

–

REFERENCE

CHARGE

PUMP

HIGH-Z

AGND

DGND

CPGND

Figure 1.

Rev. F

Document Feedback

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support

www.analog.com

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

03685-001

ADF4153

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 3

Specifications..................................................................................... 4

Timing Specifications .................................................................. 5

Absolute Maximum Ratings ............................................................ 6

ESD Caution .................................................................................. 6

Pin Configurations and Function Descriptions ........................... 7

Typical Performance Characteristics ............................................. 8

Circuit Description ........................................................................... 9

Reference Input Section ............................................................... 9

RF Input Stage ............................................................................... 9

RF INT Divider ............................................................................. 9

INT, FRAC, MOD, and R Relationship ..................................... 9

RF R Counter ................................................................................ 9

Phase Frequency Detector (PFD) and Charge Pump ............ 10

MUXOUT and Lock Detect ...................................................... 10

Input Shift Registers ................................................................... 10

Program Modes .......................................................................... 10

N Divider Register, R0 ............................................................... 16

Data Sheet

R Divider Register, R1................................................................ 16

Control Register, R2 ................................................................... 16

Noise and Spur Register, R3 ...................................................... 17

Reserved Bits ............................................................................... 17

Initialization Sequence .............................................................. 18

RF Synthesizer: A Worked Example ........................................ 18

Modulus ....................................................................................... 18

Reference Doubler and Reference Divider ............................. 18

12-Bit Programmable Modulus ................................................ 18

Fastlock with Spurious Optimization ...................................... 19

Spur Mechanisms ....................................................................... 19

Spur Consistency ........................................................................ 20

Phase Resync ............................................................................... 20

Filter Design—ADIsimPLL....................................................... 20

Interfacing ................................................................................... 20

PCB Design Guidelines for Chip Scale Package .................... 21

Applications Information .............................................................. 22

Local Oscillator for a GSM Base Station Transmitter ........... 22

Outline Dimensions ....................................................................... 23

Ordering Guide .......................................................................... 24

Automotive Products ................................................................. 24

Rev. F | Page 2 of 24

Data Sheet

REVISION HISTORY

11/13—Rev. E to Rev. F

Change to I

Sink/Source Parameter, Table 1 .............................. 4

Changes to Ordering Guide ...........................................................24

7/12—Rev. D to Rev. E

Updated Outline Dimensions ........................................................23

Changes to Ordering Guide ...........................................................24

8/10—Rev. C to Rev. D

Changes to Features Section ............................................................ 1

Changes to Noise Characteristics Parameter, Table 1 .................. 5

Changes to Figure 4........................................................................... 7

Changes to Ordering Guide ...........................................................24

Added Automotive Products Section ...........................................24

10/08—Rev. B to Rev. C

Added Y Version (Throughout) ...................................................... 1

Changes to Ordering Guide ...........................................................23

08/05—Rev. A to Rev. B

Changes to Features .......................................................................... 1

Changes to Applications ................................................................... 1

Changes to Specifications ................................................................. 3

Changes to Absolute Maximum Ratings ........................................ 5

Changes to Figure 7 to Figure 9....................................................... 7

Deleted Figure 8 to Figure 10; Renumbered Sequentially ........... 8

Deleted Figure 11 and Figure 14; Renumbered Sequentially ...... 9

Changes to Table 9 ..........................................................................13

ADF4153

Added Initialization Sequence Section ........................................ 17

Changes to Fastlock with Spurious Optimization Section ........ 18

Inserted Figure 16; Renumbered Sequentially ............................ 18

Added Spur Mechanisms Section ................................................. 18

Added Table 11; Renumbered Sequentially ................................. 18

Added Spur Consistency Section .................................................. 19

Changes to Phase Resync Section ................................................. 19

Inserted Figure 17; Renumbered Sequentially ............................ 19

Deleted Spurious Signals—

Predicting Where They Will Appear Section .............................. 20

Changes to Figure 19 ...................................................................... 20

Changes to Figure 20 ...................................................................... 21

Added Applications Section .......................................................... 21

Changes to Figure 22 Caption ....................................................... 22

Changes to Ordering Guide ........................................................... 22

1/04—Rev. 0 to Rev. A

Renumbered Figures and Tables ...................................... Universal

Changes to Specifications................................................................. 3

Changes to Pin Function Description ............................................ 7

Changes to RF Power-Down Section ........................................... 17

Changes to PCB Design Guidelines for Chip Scale

Package Section ............................................................................... 21

Updated Outline Dimensions........................................................ 22

Updated Ordering Guide ............................................................... 22

7/03—Revision 0: Initial Version

Rev. F | Page 3 of 24

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