Mixed-Signal Front End
Set-Top Box, Cable Modem
AD9879
FEATURES
Low cost 3.3 V MxFE™ for
DOCSIS-, EURO-DOCSIS-, DVB-, DAVIC-compliant
set-top box and cable modem applications
232 MHz quadrature digital upconverter
12-bit direct IF DAC (TxDAC+™)
Up to 65 MHz carrier frequency DDS
Programmable sampling clock rates
16× upsampling interpolation LPF
Single-tone frequency synthesis
Analog Tx output level adjust
Direct cable amp interface
12-bit, 33 MSPS direct IF ADC
with optional video clamping input
10-bit, 33 MSPS direct IF ADC
Dual 7-bit, 16.5 MSPS sampling I/Q ADC
12-bit Σ-∆ auxiliary DAC
FUNCTIONAL BLOCK DIAGRAM
I
TX DATA
TX Q
⇑16
SINC–1
12
DAC
TX
DDS
Σ-∆
Σ-∆_OUT
CA_PORT
4
SPORT
CONTROL REGISTERS
PLL
XM/N
MCLK
2
RXIQ[3:0]
8
MUX
RXI
ADC
MUX
2
RXQ
10
ADC
RX10
RXIF[11:0]
MUX
12
ADC
MUX
02773-001
APPLICATIONS
Cable modem and satellite systems
Set-top boxes
Power line modem
PC multimedia
Digital communications
Data and video modems
QAM, OFDM, FSK modulation
AD9879
RX12
CLAMP
VIDEO
Figure 1.
GENERAL DESCRIPTION
The AD9879 is a single-supply set-top box and cable modem
mixed-signal front end. The device contains a transmit path
interpolation filter, complete quadrature digital upconverter,
and transmit DAC. The receive path contains a 12-bit ADC, a
10-bit ADC, and dual 7-bit ADCs. All internally required clocks
and an output system clock are generated by the phase-locked
loop (PLL) from a single crystal or clock input.
The transmit path interpolation filter provides an upsampling
factor of 16× with an output signal bandwidth as high as
8.3 MHz. Carrier frequencies up to 65 MHz with 26 bits of
frequency tuning resolution can be generated by the direct
digital synthesizer (DDS). The transmit DAC resolution is
12 bits and can run at sampling rates as high as 232 MSPS.
Analog output scaling from 0.0 dB to 7.5 dB in 0.5 dB steps is
available to preserve SNR when reduced output levels are
required.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
The 12-bit and 10-bit IF ADCs can convert direct IF inputs up
to 70 MHz and run at sample rates up to 33 MSPS. A video
input with an adjustable signal clamping level, along with the
10-bit ADC, allow the AD9879 to process an NTSC and a QAM
channel simultaneously.
The programmable Σ-Δ DAC can be used to control external
components, such as variable gain amplifiers (VGAs) or voltage
controlled tuners. The CA port provides an interface to the
AD8321/AD8323 or AD8322/AD8327 programmable gain
amplifier (PGA) cable drivers, enabling host processor control
via the MxFE SPORT.
The AD9879 is available in a 100-lead MQFP. It offers enhanced
receive path undersampling performance and lower cost when
compared with the pin-compatible AD9873. The AD9879 is
specified over the commercial (−40°C to +85°C) temperature
range.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
© 2005 Analog Devices, Inc. All rights reserved.
AD9879
TABLE OF CONTENTS
Specifications..................................................................................... 4
Absolute Maximum Ratings............................................................ 7
Explanation of Test Levels ........................................................... 7
Thermal Characteristics .............................................................. 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Terminology .................................................................................... 10
Theory of Operation ...................................................................... 11
Transmit Path.............................................................................. 11
Data Assembler........................................................................... 11
Interpolation Filter ..................................................................... 12
Digital Upconverter.................................................................... 12
DPLL-A Clock Distribution...................................................... 12
Clock and Oscillator Circuitry ................................................. 12
Programmable Clock Output REFCLK................................... 13
Reset and Transmit Power-Down ............................................ 14
Σ-Δ Outputs ................................................................................ 15
Register Map and Bit Definitions ................................................. 16
Register 0x00—Initialization .................................................... 17
Register 0x01—Clock Configuration....................................... 17
Register 0x02—Power-Down.................................................... 17
Registers 0x03–0x04—Σ-Δ and Flag Control......................... 17
Register 0x07—Video Input Configuration............................ 17
Register 0x08—ADC Clock Configuration ............................ 18
Register 0x0C—Die Revision.................................................... 18
Register 0x0D—Tx Frequency Tuning Words LSBs.............. 18
Register 0x0E—DAC Gain Control ......................................... 18
Register 0x0F—Tx Path Configuration ................................... 18
Registers 0x10–0x17—Carrier Frequency Tuning................. 19
Serial Interface for Register Control ............................................ 20
General Operation of the Serial Interface............................... 20
Instruction Byte .......................................................................... 20
Serial Interface Port Pin Description....................................... 20
MSB/LSB Transfers .................................................................... 20
Notes on Serial Port Operation ................................................ 21
Transmit Path (Tx) ......................................................................... 22
Transmit Timing......................................................................... 22
Data Assembler........................................................................... 22
Half-Band Filters (HBFs) .......................................................... 22
Cascaded Integrator-Comb (CIC) Filter................................. 22
Combined Filter Response........................................................ 22
Tx Signal Level Considerations ................................................ 24
Tx Throughput and Latency ..................................................... 24
Digital-to-Analog Converter .................................................... 25
Programming the AD8321/AD8323 or AD8322/AD8327 Cable
Driver Amplifier Gain Control..................................................... 26
Receive Path (Rx) ........................................................................... 27
IF10 and IF12 ADC Operation ................................................ 27
Input Signal Range and Digital Output Codes....................... 27
Driving the Inputs ...................................................................... 27
PCB Design Considerations.......................................................... 28
Component Placement .............................................................. 28
Power Planes and Decoupling .................................................. 28
Ground Planes ............................................................................ 29
Signal Routing............................................................................. 29
Outline Dimensions ....................................................................... 30
Ordering Guide .......................................................................... 30
Rev. A | Page 2 of 32
AD9879
REVISION HISTORY
6/05—Rev. 0 to Rev. A
Updated Format.................................................................. Universal
Changed OSCOUT to REFCLK....................................... Universal
Changed REF CLK to REFCLK........................................ Universal
Changes to Specifications Section................................................... 4
Changes to Figure 13 ...................................................................... 21
Changes to Equation 18.................................................................. 24
Changes to Equation 21.................................................................. 24
Changes to Outline Dimensions ................................................... 30
Changes to Ordering Guide........................................................... 30
8/02—Revision 0: Initial Version
Rev. A | Page 3 of 32
AD9879
SPECIFICATIONS
V
AS
= 3.3 V ± 5%, V
DS
= 3.3 V ± 10%, f
OSCIN
= 27 MHz, f
SYSCLK
= 216 MHz, f
MCLK
= 54 MHz (M = 8), ADC clock from OSCIN,
R
SET
= 4.02 kΩ, 75 Ω DAC load, unless otherwise noted.
Table 1.
Parameter
OSCIN AND XTAL CHARACTERISTICS
Frequency Range
Duty Cycle
Input Impedance
MCLK Cycle to Cycle Jitter
Tx DAC CHARACTERISTICS
Resolution
Maximum Sample Rate
Full-Scale Output Current
Gain Error (Using Internal Reference)
Offset Error
Reference Voltage (REFIO Level)
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
Output Capacitance
Phase Noise @ 1 kHz Offset, 42 MHz
Crystal and OSCIN Multiplier Enabled at 16×
Output Voltage Compliance Range
Wideband SFDR
5 MHz Analog Out, I
OUT
= 10 mA
65 MHz Analog Out, I
OUT
= 10 mA
Narrow-band SFDR (±1 MHz Window)
5 MHz Analog Out, I
OUT
= 10 mA
Tx MODULATOR CHARACTERISTICS
I/Q Offset
Pass-Band Amplitude Ripple (f < f
IQCLK
/8)
Pass-Band Amplitude Ripple (f < f
IQCLK
/4)
Stop-Band Response (f > f
IQCLK
× 3/4)
Tx GAIN CONTROL
Gain Step Size
Gain Step Error
Settling Time to 1% (Full-Scale Step)
IQ ADC CHARACTERISTICS
Resolution
1
Maximum Conversion Rate
Pipeline Delay
Offset Matching Between I and Q ADCs
Gain Matching Between I and Q ADCs
Analog Input
Input Voltage Range
1
Input Capacitance
Differential Input Resistance
AC Performance (A
IN
= 0.5 dBFS, f
IN
= 5 MHz)
Effective Number of Bits (ENOB)
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)
Spurious-Free Dynamic Range (SFDR)
Temp
Full
Full
25°C
25°C
N/A
Full
Full
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Full
Full
Full
Full
Full
Full
Full
Full
25°C
25°C
25°C
N/A
Full
N/A
Full
Full
Full
25°C
25°C
25°C
25°C
25°C
25°C
Test Level
II
II
III
III
N/A
II
II
I
I
I
III
III
III
III
II
III
III
III
II
II
II
II
III
III
III
N/A
II
N/A
III
III
III
III
III
I
I
I
I
5.00
34.7
41.3
Min
3
35
Typ
Max
29
65
Unit
MHz
%
MΩ||pF
ps rms
Bits
MHz
mA
% FS
% FS
V
LSB
LSB
pF
dBc/Hz
V
dBc
dBc
dBc
dB
dB
dB
dB
dB
dB
µs
Bits
MHz
ADC cycles
LSBs
LSBs
Vppd
pF
kΩ
Bits
dB
dB
dB
50
100||3
6
12
232
4
−2.0
1.18
10
−1.0
±1.0
1.23
±2.5
±8
5
−110
20
+2.0
1.28
−0.5
60.8
44.0
65.4
50
66.9
46.2
72.3
55
+1.5
±0.1
±0.5
−63
0.5
<0.05
1.8
6
14.5
3.5
±4.0
±2.0
1
2.0
4
5.8
36.5
−50
51
−36.2
Rev. A | Page 4 of 32
AD9879
Parameter
10-BIT ADC CHARACTERISTICS
Resolution
Maximum Conversion Rate
Pipeline Delay
Analog Input
Input Voltage Range
Input Capacitance
Differential Input Resistance
Reference Voltage Error
(REFT10–REFB10) –1 V
AC Performance (A
IN
= –0.5 dBFS, f
IN
= 5 MHz)
ADC Sample Clock Source = OSCIN
Signal-to-Noise and Distortion (SINAD)
Effective Number of Bits (ENOB)
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)
Spurious-Free Dynamic Range (SFDR)
AC Performance (A
IN
= −0.5 dBFS, f
IN
= 50 MHz)
ADC Sample Clock Source = OSCIN
Signal-to-Noise and Distortion (SINAD)
Effective Number of Bits (ENOB)
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)
Spurious-Free Dynamic Range (SFDR)
12-BIT ADC CHARACTERISTICS
Resolution
Maximum Conversion Rate
Pipeline Delay
Analog Input
Input Voltage Range
Input Capacitance
Differential Input Resistance
Reference Voltage Error
(REFT12–REFB12) −1 V
AC Performance (A
IN
= −0.5 dBFS, f
IN
= 5 MHz)
ADC Sample Clock Source = OSCIN
Signal-to-Noise and Distortion (SINAD)
Effective Number of Bits (ENOB)
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)
Spurious-Free Dynamic Range (SFDR)
AC Performance (A
IN
= −0.5 dBFS, f
IN
= 50 MHz)
ADC Sample Clock Source = OSCIN
Signal-to-Noise and Distortion (SINAD)
Effective Number of Bits (ENOB)
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)
Spurious-Free Dynamic Range (SFDR)
VIDEO CLAMP PERFORMANCE
(A
IN
= −0.5 dBFS, f = 5 MHz)
ADC Sample Clock = OSCIN
Signal-to-Noise and Distortion (SINAD)
Effective Number of Bits (ENOB)
Temp
N/A
Full
N/A
Full
25°C
25°C
Full
Test Level
N/A
II
N/A
III
III
II
I
Min
Typ
10
29
4.5
2.0
2
4
±4
±200
Max
Unit
Bits
MHz
ADC cycles
Vppd
pF
kΩ
mV
Full
Full
Full
Full
Full
II
II
II
II
II
58.3
9.4
58.6
65.7
59.9
9.65
60
−73
76
−62
dB
Bits
dB
dB
dB
Full
Full
Full
Full
Full
N/A
Full
N/A
Full
25°C
25°C
Full
II
II
II
II
II
N/A
II
N/A
III
III
III
I
57.7
9.29
57.8
−61.4
64
59.0
9.51
59.1
−75
78
12
dB
Bits
dB
dB
dB
Bits
MHz
ADC cycles
Vppd
pF
kΩ
±200
mV
29
5.5
2
2
4
±16
Full
Full
Full
Full
Full
II
II
II
II
II
60.0
9.67
60.3
64.7
65.2
10.53
65.6
−76.6
79
−58.7
dB
Bits
dB
dB
dB
Full
Full
Full
Full
Full
II
II
II
II
II
59.5
9.59
59.7
63.8
62.7
10.1
63.0
−75.5
79
−60.5
dB
Bits
dB
dB
dB
Full
Full
II
II
43.9
7.0
50.6
8.1
dB
Bits
Rev. A | Page 5 of 32
京公网安备 11010802033920号
EEWORLD
