Complete 12-Bit 40 MSPS
Imaging Signal Processor
AD9821
FEATURES
Differential Sensor Input with 1 V p-p Input Range
0 dB to 36 dB 10-Bit Variable Gain Amplifier (VGA)
Low Noise Optical Black Clamp Circuit
Analog Preblanking Function
12-Bit 40 MSPS A/D Converter (ADC)
3-Wire Serial Digital Interface
3 V Single-Supply Operation
Low Power: 150 mW @ 3 V Supply
48-Lead LQFP Package
APPLICATIONS
Digital Still Cameras Using CMOS Imagers
Industrial/Scientific Imaging
GENERAL DESCRIPTION
The AD9821 is a complete analog signal processor for imaging
applications that do not require Correlated Double Sampling
(CDS). It features a 40 MHz single-channel architecture designed
to sample and condition the outputs of CMOS imagers and CCD
arrays already containing on-chip CDS. The AD9821’s signal
chain consists of a differential input sample-and-hold amplifier
(SHA), digitally controlled variable gain amplifier (VGA), black
level clamp, and a 12-bit ADC.
The internal registers are programmed through a 3-wire serial
digital interface. Programmable features include gain adjust-
ment, black level adjustment, and power-down modes.
The AD9821 operates from a single 3 V power supply, typically
dissipates 150 mW, and is packaged in a 48-lead LQFP.
FUNCTIONAL BLOCK DIAGRAM
AVDD
AVSS
VRT
VRB
PBLK
AD9821
0dB ~ 36dB
VIN+
VIN–
+
SHA
–
VGA
BAND GAP
REFERENCE
DRVDD
DRVSS
12
DOUT
12-BIT
ADC
BYP1
10
CLP
CLPOB
8
INTERNAL
REGISTERS
BLK CLAMP
LEVEL
DVDD
DIGITAL
INTERFACE
DVSS
SL
SCK
SDATA
DATACLK
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
AD9821–SPECIFICATIONS
GENERAL SPECIFICATIONS
Parameter
TEMPERATURE RANGE
Operating
Storage
POWER SUPPLY VOLTAGE
Analog, Digital, Digital Driver
POWER CONSUMPTION
Normal Operation
Power-Down Modes
Standby
Total Power-Down
MAXIMUM CLOCK RATE
A/D CONVERTER
Resolution
Differential Nonlinearity (DNL)
No Missing Codes
Full-Scale Input Voltage
Data Output Coding
VOLTAGE REFERENCE
Reference Top Voltage (VRT)
Reference Bottom Voltage (VRB)
Specifications subject to change without notice.
(T
MIN
to T
MAX
, AVDD = DVDD = 3.0 V, f
DATACLK
= 40 MHz, unless otherwise noted.)
Min
–20
–65
2.7
Typ
Max
+85
+150
3.6
Unit
°C
°C
V
(Specified under Each Mode of Operation)
5
1
40
12
±
0.5
12
2.0
Straight Binary
2.0
1.0
mW
mW
MHz
Bits
LSB
Bits Guaranteed
V
V
V
DIGITAL SPECIFICATIONS
(DRVDD = 2.7 V, C = 20 pF, unless otherwise noted.)
L
Parameter
LOGIC INPUTS
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
LOGIC OUTPUTS
High Level Output Voltage, I
OH
= 2 mA
Low Level Output Voltage, I
OL
= 2 mA
Specifications subject to change without notice.
Symbol
V
IH
V
IL
I
IH
I
IL
C
IN
V
OH
V
OL
Min
2.1
Typ
Max
Unit
V
V
µA
µA
pF
V
V
0.6
10
10
10
2.2
0.5
–2–
REV. 0
AD9821
IMAGER-MODE SPECIFICATIONS
(T
Parameter
P
OWER CONSUMPTION
MAXIMUM CLOCK RATE
ANALOG INPUTS (VIN+, VIN–)
Input Common-Mode Range*
Max Input Amplitude*
Max Optical Black Pixel Amplitude*
VARIABLE GAIN AMPLIFIER (VGA)
Gain Control Resolution
Gain Monotonicity
Gain Range
Min Gain (VGA Gain Code 00)
Max Gain (VGA Gain Code 1023)
BLACK LEVEL CLAMP
Clamp Level Resolution
Clamp Level
Min Clamp Level
Max Clamp Level
SYSTEM PERFORMANCE
Gain Accuracy
Min Gain
Max Gain
Peak Nonlinearity, 500 mV Input
Total Output Noise
Power Supply Rejection (PSR)
POWER-UP RECOVERY TIME
Reference Standby Mode
Total Power-Down Mode
Power-Off Condition
*Input
Signal Characteristics defined as follows:
+1.8V
1V p-p MAX
INPUT SIGNAL RANGE
VIN+
VIN–
GND
30mV MAX
OB PIXEL
MIN
to T
MAX
, AVDD = DVDD = 3.0 V, f
DATACLK
= 40 MHz, unless otherwise noted.)
Typ
150
Min
Max
Unit
mW
MHz
Notes
See TPC 1 for Power vs. Sample Rate
40
0
1.0
±
30
1024
Guaranteed
0
36
256
0
255
1.8
V
V p-p
mV
Steps
Linear operating range for VIN+, VIN–
Defined as VIN+ minus VIN–
For stable Clamp at max VGA gain
See Figure 11 for VGA Gain Curve
dB
dB
Steps
Measured at ADC Output
LSB
LSB
Specifications Include Entire Signal Chain
–1
34.5
0
35.5
0.3
0.5
40
1
3
10
+1
36.5
dB
dB
%
LSB rms
dB
ms
ms
ms
12 dB Gain Applied
AC Grounded Input, 6 dB Gain Applied
Measured with Step Change on Supply
Normal Clock Signals Applied
INPUT
CM RANGE
Specifications subject to change without notice.
REV. 0
–3–
AD9821
TIMING SPECIFICATIONS
(C = 20 pF, f
L
SAMP
= 40 MHz, Imager-Mode Timing in Figures 5 and 6, Serial Timing in Figures 7–9)
Symbol
t
CONV
t
ADC
t
COB
t
ID
t
OD
t
H
Min
25
11
2
Typ
25
12.5
20
3.0
13
7.6
9
16
Max
Unit
ns
ns
Pixels
ns
ns
ns
Cycles
MHz
ns
ns
ns
ns
ns
Parameter
SAMPLE CLOCKS
DATACLK Clock Period
DATACLK Hi/Low Pulsewidth
CLPOB Pulsewidth*
Internal Clock Delay
DATA OUTPUTS
Output Delay
Output Hold Time
Pipeline Delay
SERIAL INTERFACE
Maximum SCK Frequency
SL to SCK Setup Time
SCK to SL Hold Time
SDATA Valid to SCK Rising Edge Setup
SCK Falling Edge to SDATA Valid Hold
SCK Falling Edge to SDATA Valid Read
Specifications subject to change without notice.
7.0
f
SCLK
t
LS
t
LH
t
DS
t
DH
t
DV
10
10
10
10
10
10
*Minimum
CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp performance.
ABSOLUTE MAXIMUM RATINGS
With
Respect
To
ORDERING GUIDE
Model
Min
Max
Unit
Temperature
Range
–20°C to +85°C
Package
Description
Thin Plastic
Quad Flatpack
(LQFP)
Package
Option
ST-48
Parameter
AD9821KST
AVDD1, AVDD2
DVDD1, DVDD2
DRVDD
Digital Outputs
DATACLK
CLPOB, PBLK
SCK, SL, SDATA
VRT, VRB
BYP1, VIN
Junction Temperature
Lead Temperature
(10 sec)
AVSS
DVSS
DRVSS
DRVSS
DVSS
DVSS
DVSS
AVSS
AVSS
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
+3.9
+3.9
+3.9
DRVDD + 0.3
DVDD + 0.3
DVDD + 0.3
DVDD + 0.3
AVDD + 0.3
AVDD + 0.3
150
300
V
V
V
V
V
V
V
V
V
°C
°C
THERMAL CHARACTERISTICS
Thermal Resistance
48-Lead LQFP Package
θ
JA
= 56°C/W
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD9821 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
–4–
REV. 0
AD9821
PIN CONFIGURATION
SDATA
DVDD2
DVSS
STBY
SCK
VRB
VRT
NC
NC
NC
48 47 46 45 44 43 42 41 40 39 38 37
(LSB) D0
1
D1
2
D2
3
D3
4
D4
5
D5
6
D6
7
D7
8
D8
9
D9
10
D10
11
(MSB) D11
12
NC = NO CONNECT
NC
36
35
34
33
SL
PIN 1
IDENTIFIER
TEST
AVSS
TEST
AVDD2
BYP1
VIN–
VIN+
TEST
TEST
AVDD1
AVSS
AVSS
AD9821
TOP VIEW
(Not to Scale)
32
31
30
29
28
27
26
25
13 14 15 16 17 18 19 20 21 22 23 24
NC
DRVDD
DVDD1
CLPOB
DRVSS
TEST
TEST
DATACLK
PIN FUNCTION DESCRIPTIONS
Pin Number
Mnemonic
Type
Description
1–12
13
14
15, 41
16
17
18, 24, 37, 42, 47, 48
19
20
21–23
25, 26, 35
27
28, 29
30
31
32
33
34, 36
38
39
40
43
44
45
46
D0–D11
DRVDD
DRVSS
DVSS
DATACLK
DVDD1
NC
PBLK
CLPOB
TEST
AVSS
AVDD1
TEST
VIN+
VIN–
BYP1
AVDD2
TEST
VRT
VRB
DVDD2
STBY
SL
SDATA
SCK
DO
P
P
P
DI
P
NC
DI
DI
DI
P
P
AO
AI
AI
AO
P
AI
AO
AO
P
DI
DI
DI
DI
DVSS
PBLK
Digital Data Outputs
Digital Output Driver Supply
Digital Output Driver Ground
Digital Ground
Digital Data Output Latch Clock
Digital Supply
Internally Not Connected. May be Tied High or Low.
Preblanking Clock Input
Black Level Clamp Clock Input
Test Use Only. Tie to VDD or VSS.
Analog Ground
Analog Supply
Test Use Only. Tie to VDD or VSS.
Positive Analog Input for Imager Signal
Negative Analog Input for Imager Signal
Internal Bias Level Decoupling
Analog Supply
Test Use Only. Tie to VDD or VSS.
ADC Top Reference Voltage Decoupling
ADC Bottom Reference Voltage Decoupling
Digital Supply
Standby Mode, Active High. Same as Total Power-Down Mode.
Serial Digital Interface Load Pulse
Serial Digital Interface Data
Serial Digital Interface Clock
TYPE: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power.
REV. 0
–5–
TEST
NC
Embedded System
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