Data Sheet
FEATURES
Dual 8-/10-/12-/14-/16-Bit
250 MSPS Digital-to-Analog Converters
AD9741/AD9743/AD9745/AD9746/AD9747
GENERAL DESCRIPTION
The
AD9741/AD9743/AD9745/AD9746/AD9747
are pin-
compatible, high dynamic range, dual digital-to-analog
converters (DACs) with 8-/10-/12-/ 14-/16-bit resolutions
and sample rates of up to 250 MSPS. The devices include
specific features for direct conversion transmit applications,
including gain and offset compensation, and they interface
seamlessly with analog quadrature modulators, such as the
ADL5370.
A proprietary, dynamic output architecture permits synthesis
of analog outputs even above Nyquist by shifting energy away
from the fundamental and into the image frequency.
Full programmability is provided through a serial peripheral
interface (SPI) port. In addition, some pin-programmable
features are offered for those applications without a controller.
High dynamic range, dual DACs
Low noise and intermodulation distortion
Single carrier WCDMA ACLR = 80 dBc at 61.44 MHz IF
Innovative switching output stage permits useable outputs
beyond Nyquist frequency
LVCMOS inputs with dual-port or optional interleaved
single-port operation
Differential analog current outputs are programmable from
8.6 mA to 31.7 mA full scale
Auxiliary 10-bit current DACs with source/sink capability for
external offset nulling
Internal 1.2 V precision reference voltage source
Operates from 1.8 V and 3.3 V supplies
315 mW power dissipation
Small footprint, Pb-free, 72-pin LFCSP
APPLICATIONS
Wireless infrastructure:
WCDMA, CDMA2000, TD-SCDMA, WiMAX
Wideband communications:
LMDS/MMDS, point-to-point
Instrumentation:
RF signal generators, arbitrary waveform generators
PRODUCT HIGHLIGHTS
1.
2.
3.
Low noise and intermodulation distortion (IMD) enables
high quality synthesis of wideband signals.
Proprietary switching output for enhanced dynamic
performance.
Programmable current outputs and dual auxiliary DACs
provide flexibility and system enhancements.
FUNCTIONAL BLOCK DIAGRAM
CLKP
CLKN
16-BIT
DAC1
INTERFACE LOGIC
PID<15:0>
10
CMOS
INTERFACE
GAIN
DAC
GAIN
DAC
INTERNAL
REFERENCE
AND
BIAS
OFFSET
DAC
OFFSET
DAC
AUX1P
AUX1N
AUX2P
AUX2N
06569-001
IOUT1P
IOUT1N
IOUT2P
IOUT2N
16-BIT
DAC2
P2D<15:0>
SERIAL
PERIPHERAL
INTERFACE
REFIO
SDIO
SCLK
SDO
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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AD9741/AD9743/AD9745/AD9746/AD9747
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
DC Specifications ......................................................................... 3
AC Specifications.......................................................................... 5
Digital and Timing Specifications .............................................. 7
Absolute Maximum Ratings............................................................ 8
Thermal Resistance ...................................................................... 8
ESD Caution .................................................................................. 8
Pin Configurations and Function Descriptions ........................... 9
Typical Performance Characteristics ........................................... 14
Terminology .................................................................................... 17
Theory of Operation ...................................................................... 18
Serial Peripheral Interface ......................................................... 18
General Operation of the Serial Interface ............................... 18
Data Sheet
Instruction Byte .......................................................................... 18
MSB/LSB Transfers .................................................................... 19
Serial Interface Port Pin Descriptions ..................................... 19
SPI Register Map ............................................................................ 20
SPI Register Descriptions .............................................................. 21
Digital Inputs and Outputs ........................................................... 22
Input Data Timing ..................................................................... 22
Dual-Port Mode Timing ........................................................... 22
Single-Port Mode Timing ......................................................... 22
SPI Port, Reset, and Pin Mode .................................................. 22
Driving the DAC Clock Input .................................................. 23
Full-Scale Current Generation ................................................. 23
DAC Transfer Function ............................................................. 24
Analog Modes of Operation ..................................................... 24
Auxiliary DACS .......................................................................... 25
Power Dissipation....................................................................... 25
Outline Dimensions ....................................................................... 27
Ordering Guide .......................................................................... 27
REVISION HISTORY
1/14—Rev. 0 to Rev. A
Changes to Table 15 ........................................................................ 21
Updated Outline Dimensions ....................................................... 27
Changes to Ordering Guide .......................................................... 27
5/07—Revision 0: Initial Version
Rev. A | Page 2 of 28
Data Sheet
SPECIFICATIONS
DC SPECIFICATIONS
AD9741/AD9743/AD9745/AD9746/AD9747
T
MIN
to T
MAX
, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, I
FS
= 20 mA, full-scale digital input, maximum
sample rate, unless otherwise noted.
Table 1.
AD9741, AD9743,
and
AD9745
Parameter
RESOLUTION
ACCURACY
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
MAIN DAC OUTPUTS
Offset Error
Offset Error Temperature Coefficient
Gain Error
Gain Error Temperature Coefficient
Gain Matching (DAC1 to DAC2)
Full-Scale Output Current
Output Compliance Voltage
Output Resistance
AUXILIARY DAC OUTPUTS
Resolution
Full-Scale Output Current
Output Compliance Voltage Range—Sink Current
Output Compliance Voltage Range—Source Current
Output Resistance
Monotonicity
REFERENCE INPUT/OUTPUT
Output Voltage
Output Voltage Temperature Coefficient
External Input Voltage Range
Input or Output Resistance
POWER SUPPLY VOLTAGES
AVDD33, DVDD33
CVDD18, DVDD18
POWER SUPPLY CURRENTS
I
AVDD33
I
DVDD33
I
CVDD18
I
DVDD18
POWER DISSIPATION
f
DAC
= 250 MSPS, f
OUT
= 20 MHz
DAC Outputs Disabled
Full Device Power-Down
OPERATING TEMPERATURE
Min
AD9741
Typ
Max
8
±0.03
±0.05
±0.001
1.0
±2.0
100
±1.0
8.6
−1.0
10
10
−2.0
0.8
0
1
10
1.2
10
1.15
5
3.13
1.70
56
10
18
28
300
115
3
−40
3.47
1.90
60
14
22
32
345
3.13
1.70
56
10
18
29
300
115
3
−40
1.3
1.15
5
3.47
1.90
60
14
22
33
345
3.13
1.70
56
11
18
30
305
120
3
−40
10
1.2
10
1.3
1.15
5
3.47
1.90
60
15
22
34
350
+2.0
1.6
1.6
−2.0
0.8
0
1
10
1.2
10
1.3
31.7
+1.0
8.6
−1.0
10
10
+2.0
1.6
1.6
−2.0
0.8
0
1
Min
AD9743
Typ
Max
10
±0.05
±0.10
±0.001
1.0
±2.0
100
±1.0
31.7
+1.0
8.6
−1.0
10
10
+2.0
1.6
1.6
Min
AD9745
Typ
Max
12
±0.13
±0.25
±0.001
1.0
±2.0
100
±1.0
31.7
+1.0
Unit
Bits
LSB
LSB
%FSR
ppm/°C
%FSR
ppm/°C
%FSR
mA
V
MΩ
Bits
mA
V
V
MΩ
Bits
V
ppm/°C
V
kΩ
V
V
mA
mA
mA
mA
mW
mW
mW
°C
+85
+85
+85
Rev. A | Page 3 of 28
AD9741/AD9743/AD9745/AD9746/AD9747
Data Sheet
T
MIN
to T
MAX
, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, I
FS
= 20 mA, full-scale digital input, maximum
sample rate, unless otherwise noted. The
AD9745
is repeated in Table 2 so the user can compare it with all other parts.
Table 2.
AD9745, AD9746,
and
AD9747
Parameter
RESOLUTION
ACCURACY
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
MAIN DAC OUTPUTS
Offset Error
Offset Error Temperature Coefficient
Gain Error
Gain Error Temperature Coefficient
Gain Matching (DAC1 to DAC2)
Full-Scale Output Current
Output Compliance Voltage
Output Resistance
AUXILIARY DAC OUTPUTS
Resolution
Full-Scale Output Current
Output Compliance Voltage Range—Sink Current
Output Compliance Voltage Range—Source Current
Output Resistance
Monotonicity
REFERENCE INPUT/OUTPUT
Output Voltage
Output Voltage Temperature Coefficient
External Input Voltage Range
Input or Output Resistance
POWER SUPPLY VOLTAGES
AVDD33, DVDD33
CVDD18, DVDD18
POWER SUPPLY CURRENTS
I
AVDD33
I
DVDD33
I
CVDD18
I
DVDD18
POWER DISSIPATION
f
DAC
= 250 MSPS, f
OUT
= 20 MHz
DAC Outputs Disabled
Full Device Power-Down
OPERATING TEMPERATURE
Min
AD9745
Typ
Max
12
±0.13
±0.25
±0.001
0.1
±2.0
100
±1.0
8.6
−1.0
10
10
−2.0
0.8
0
1
10
1.2
10
1.15
5
3.13
1.70
56
11
18
30
305
120
3
−40
3.47
1.90
60
15
22
34
350
3.13
1.70
56
12
18
31
310
125
3
−40
1.3
1.15
5
3.47
1.90
60
16
22
35
355
3.13
1.70
56
12
18
32
310
125
3
−40
10
1.2
10
1.3
1.15
5
3.47
1.90
60
16
22
36
355
+2.0
1.6
1.6
−2.0
0.8
0
1
10
1.2
10
1.3
31.7
+1.0
8.6
−1.0
10
10
+2.0
1.6
1.6
−2.0
0.8
0
1
Min
AD9746
Typ
Max
14
±0.5
±1.0
±0.001
0.1
±2.0
100
±1.0
31.7
+1.0
8.6
−1.0
10
10
+2.0
1.6
1.6
Min
AD9747
Typ
Max
16
±2.0
±4.0
±0.001
0.1
±2.0
100
±1.0
31.7
+1.0
Unit
Bits
LSB
LSB
%FSR
ppm/°C
%FSR
ppm/°C
%FSR
mA
V
MΩ
Bits
mA
V
V
MΩ
Bits
V
ppm/°C
V
kΩ
V
V
mA
mA
mA
mA
mW
mW
mW
°C
+85
+85
+85
Rev. A | Page 4 of 28
Data Sheet
AC SPECIFICATIONS
AD9741/AD9743/AD9745/AD9746/AD9747
T
MIN
to T
MAX
, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, I
FS
= 20 mA, full-scale digital input, maximum
sample rate, unless otherwise noted.
Table 3.
AD9741, AD9743,
and
AD9745
Parameter
SPURIOUS FREE DYNAMIC RANGE (SFDR)
f
DAC
= 250 MSPS, f
OUT
= 20 MHz
f
DAC
= 250 MSPS, f
OUT
= 70 MHz
f
DAC
= 250 MSPS, f
OUT
= 180 MHz
1
INTERMODULATION DISTORTION (IMD)
f
DAC
= 250 MSPS, f
OUT
= 20 MHz
f
DAC
= 250 MSPS, f
OUT
= 70 MHz
f
DAC
= 250 MSPS, f
OUT
= 180 MHz
1
CROSSTALK
f
DAC
= 250 MSPS, f
OUT
= 20 MHz
f
DAC
= 250 MSPS, f
OUT
= 70 MHz
f
DAC
= 250 MSPS, f
OUT
= 180 MHz
1
ADJACENT CHANNEL LEAKAGE RATIO (ACLR) SINGLE
CARRIER WCDMA
f
DAC
= 245.76 MSPS, f
OUT
= 15.36 MHz
f
DAC
= 245.76 MSPS, f
OUT
= 61.44 MHz
f
DAC
= 245.76 MSPS, f
OUT
= 184.32 MHz
1
NOISE SPECTRAL DENSITY (NSD)
f
DAC
= 245.76 MSPS, f
OUT
= 15.36 MHz
f
DAC
= 245.76 MSPS, f
OUT
= 61.44 MHz
f
DAC
= 245.76 MSPS, f
OUT
= 184.32 MHz
1
1
AD9741
Min Typ
Max
70
70
64
80
80
72
80
80
80
AD9743
Min Typ
Max
80
70
64
80
80
72
80
80
80
AD9745
Min Typ
Max
82
70
66
86
80
74
80
80
80
Unit
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
54
54
54
−132
−132
−135
66
66
64
−144
−144
−147
76
76
72
−155
−155
−155
dBc
dBc
dBc
dBm/Hz
dBm/Hz
dBm/Hz
Mix Mode.
Rev. A | Page 5 of 28
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