EP9445-50 datasheet, PDF - EEWORLD Datasheet

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EP9445-50: Description16 Pin DIL 5 Tap 10K ECL Compatible Active Delay Lines; Categorylogic logic; File Size16KB，1 Pages; ManufacturerPCA Electronics Inc.; Websitehttp://www.pca.com/

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EP9445-50 Overview

16 Pin DIL 5 Tap 10K ECL Compatible Active Delay Lines

EP9445-50 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	PCA Electronics Inc.
Objectid	1413164320
Parts packaging code	DIP
package instruction	DIP, DIP16,.3
Contacts	16/9
Reach Compliance Code	compli
compound_id	5192368
Other features	TAP TO TAP DELAY TOL. [NS] VARIES; MAX RISE TIME CAPTURED
series	10K
Input frequency maximum value (fmax)	1.33333 MHz
JESD-30 code	R-XDIP-T9
JESD-609 code	e0
Logic integrated circuit type	ACTIVE DELAY LINE
Humidity sensitivity level	3
Number of functions	1
Number of taps/steps	5
Number of terminals	9
Maximum operating temperature	80 °C
Minimum operating temperature	-30 °C
Output characteristics	OPEN-EMITTER
Output polarity	TRUE
Package body material	UNSPECIFIED
encapsulated code	DIP
Encapsulate equivalent code	DIP16,.3
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Maximum supply current (ICC)	50 mA
programmable delay line	NO
Prop。Delay @ Nom-Su	50 ns
Certification status	Not Qualified
Maximum seat height	6.985 mm
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	ECL
Temperature level	COMMERCIAL EXTENDED
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
Total delay nominal (td)	50 ns
width	7.62 mm

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16 Pin DIL 5 Tap 10K ECL Compatible Active Delay Lines

TAP 1

nS ±5%

3.0 Typ†

3.0 Typ

4 ± 1.0

5 ± 1.0

6 ± 1.0

8 ± 1.0

10 ± 1.0

15 ± 1.5

20 ± 2.0

30 ± 2.0

100

120

140

160

180

200

TAP 2

nS ±5%

4 ± 0.3

5 ± 0.5

6 ± 0.5

8 ± 0.5

10 ± 1.0

12 ± 1.0

16 ± 1.5

20 ± 2.0

30 ± 2.0

100

120

140

160

180

200

240

280

320

360

400

TAP 3

nS ±5%

5 ± 0.3

7 ± 0.5

9 ± 0.5

12 ± 1.0

15 ± 1.5

18 ± 1.5

24 ± 2.0

30 ± 2.0

120

150

180

210

240

270

300

360

420

480

520

600

TAP 4

nS ±5%

6 ± 0.3

9 ± 0.5

12 ± 1.0

16 ± 1.5

20 ± 2.0

24 ± 2.0

32 ± 2.0

120

160

200

240

280

320

360

400

480

560

640

720

800

OUTPUT

nS ±5%

7 ± 0.3

11 ± 0.5

15 ± 1.5

20 ± 2.0

25 ± 2.0

30 ± 2.0

100

150

200

250

300

350

400

450

500

600

700

800

900

1000

RISE TIME

nS MAX

PART

NUMBER

EP9445-7

EP9445-11

EP9445-15

EP9445-20

EP9445-25

EP9445-30

EP9445-40

EP9445-50

EP9445-75

EP9445-100

EP9445-150

EP9445-200

EP9445-250

EP9445-300

EP9445-350

EP9445-400

EP9445-450

EP9445-500

EP9445-600

EP9445-700

EP9445-800

EP9445-900

EP9445-1000

Delay time measured at - 1.3V, no load

Delay times referenced from input to leading edges

†Inherent delay

Rise time output measured from 20% to 80%

Output terminated (externally) with 50Ω to - 2.0Vdc

DC Electrical Characteristics

Parameter

*Test Conditions

VOH

VOHT

VOLT

VOH

IIH

IIL

IEE

High-Level Output Voltage

High-Level Output Threshold

Voltage

Low-Level Output Threshold

Voltage

Low-Level Output Voltage

High-Level Input Current

Low-Level Input Current

VEE Supply Current

VIL = Min

Schematic

Min Max Unit

-960

-980

-1630

-1650

265

0.5

VEE

VIH = Max

VIL = Min

µA

1, 16

* (VCC1 = VCC2 = GRD, V = -5.2V ± 0.01V, Output Loading with 50Ω to -2.0V ± 0.01V)

Recommended

Operating Conditions

Min

VEE

VCC

VIH

VIHT

VILT

VIL

PW*

Supply Voltage (Negative)

Circuit Ground (Pins 1 and 16)

HIgh-Level Input Voltage

High-Level Input Threshold Voltage

Low-Level Input Threshold Voltage

Low-Level Input Voltage

Pulse Width of Total Delay

Duty Cycle

Operating Free-Air Temperature

4.94

-980

Package Dimensions

Max

5.46

-1105

-1475

-1630

300

-30

+80

Unit

°C

White Dot

Pin#1

PCA

EP9445-7

Date Code

.800 Max.

.275

Max.

.010 x .018

.100

.020

.040

.130 Typ.

.300

.400

Max.

*These two values are inter-dependent.

Input Pulse Test Conditions @ 25° C

VIN

TRI

PRR

VEE

Pulse Input Voltage

Pulse Width of Total Delay

Pulse Rise Time (20% to 80%)

Pulse Spacing

Supply Voltage

-1.0V (-0.75 to -1.75V)

3x Total Delay

2 nS

10x Total Td

-5.2V

QAF-CSO1 Rev. B 8/25/94

DSD9445 8/25/94

Unless Otherwise Noted Dimensions in Inches

Tolerances:

Fractional = ± 1/32

.XX = ± .030

.XXX = ± .010

ELECTRONICS

INC.

16799 SCHOENBORN ST.

NORTH HILLS, CA 91343

TEL: (818) 892-0761

FAX: (818) 894-5791

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