EPA1145-900 datasheet, PDF - EEWORLD Datasheet

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EPA1145-900: Description14 Pin DIP 5 Tap Fast-TTL Logic Compatible Active Delay Lines; Categorylogic logic; File Size16KB，1 Pages; ManufacturerPCA Electronics Inc.; Websitehttp://www.pca.com/

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EPA1145-900 Overview

14 Pin DIP 5 Tap Fast-TTL Logic Compatible Active Delay Lines

EPA1145-900 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	PCA Electronics Inc.
Parts packaging code	DIP
package instruction	DIP, DIP14,.3
Contacts	14/8
Reach Compliance Code	compliant
Other features	MAX RISE TIME CAPTURED
series	F
Input frequency maximum value (fmax)	1.11111 MHz
JESD-30 code	R-PDIP-T8
JESD-609 code	e0
Logic integrated circuit type	ACTIVE DELAY LINE
Humidity sensitivity level	3
Number of functions	1
Number of taps/steps	5
Number of terminals	8
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Encapsulate equivalent code	DIP14,.3
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Maximum supply current (ICC)	50 mA
programmable delay line	NO
Prop。Delay @ Nom-Sup	900 ns
Certification status	Not Qualified
Maximum seat height	6.35 mm
Maximum supply voltage (Vsup)	5.25 V
Minimum supply voltage (Vsup)	4.75 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	TTL
Temperature level	MILITARY
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
Total delay nominal (td)	900 ns
width	7.62 mm
Base Number Matches	1

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14 Pin DIP 5 Tap Fast-TTL Logic Compatible

Active Delay Lines

TAP DELAYS

±5% or ±2 nS†

*3±1, 1±.5, 2±.5, 3±.5

*3±1, 1.5±.5, 3±.5, 4.5±.5

*3±1, 2±.5, 4±.5,6±.5

*3±1, 6±1.5, 9, 12

4, 8, 12, 16

5, 10, 15, 20

6, 12, 18, 24

8, 16, 24, 32

10, 20, 30, 40

12, 24, 36, 48

15, 30, 45, 60

20, 40, 60, 80

25, 50, 75, 100

30, 60, 90, 120

TOTAL DELAYS

±5% or ±2 nS†

100

125

150

PART

NUMBER

EPA1145-4

EPA1145-6

EPA1145-8

EPA1145-15

EPA1145-20

EPA1145-25

EPA1145-30

EPA1145-40

EPA1145-50

EPA1145-60

EPA1145-75

EPA1145-100

EPA1145-125

EPA1145-150

TAP DELAYS

±5% or ±2 nS†

35, 70, 105, 140

40, 80, 120, 160

45, 90, 135, 180

50, 100, 150, 200

60, 120, 180, 240

70, 140, 210, 280

80, 160, 240, 320

90, 180, 270, 360

100, 200, 300, 400

120, 240, 360, 480

140, 280, 420, 560

160, 320, 480, 640

180, 360, 540, 720

200, 400, 600, 800

TOTAL DELAYS

±5% or ±2 nS†

175

200

225

250

300

350

400

450

500

600

700

800

900

1000

PART

NUMBER

EPA1145-175

EPA1145-200

EPA1145-225

EPA1145-250

EPA1145-300

EPA1145-350

EPA1145-400

EPA1145-450

EPA1145-500

EPA1145-600

EPA1145-700

EPA1145-800

EPA1145-900

EPA1145-1000

†Whichever

is greater. Delay times referenced from input to leading edges at 25°C, 5.0V, with no load.

* First tap is inherent delay (3 ± 1 nS), all other taps are measured referenced from first tap.

DC Electrical Characteristics

Parameter

Test Conditions

VOH

VOL

VIK

IIH

High-Level Output Voltage

Low-Level Output Voltage

Input Clamp Voltage

High-Level Input Current

Schematic

Min Max Unit

0.5

-1.2

1.0

-0.6

-150

µA

VCC = min. V IL = max. I OH = max 2.7

VCC = min. V IH = min. I OL = max

VCC = min. II = II K

VCC = max. V IN = 2.7V

VCC = max. V IN = 5.25V

IIL

Low-Level Input Current

VCC = max. V IN = 0.5V

IOS

Short Circuit Output Current VCC = max. V OUT = 0.

-40

(One output at a time)

ICCH High-Level Supply Current

VCC = max. V IN = OPEN

ICCL Low-Level Supply Current

VCC = max. V IN = 0

TRO Output Rise Time

≤

500 nS (0.75 to 2.4 Volts)

Td > 500 nS

Fanout High-Level Output

VCC = max. V OH = 2.7V

Fanout Low-Level Output

VCC = max. V OL = 0.5V

VCC

OUTPUT

INPUT 1

20 TTL LOAD

10 TTL LOAD

7 GROUND

Recommended

Operating Conditions

VCC

VIH

VIL

IIK

IOH

IOL

PW*

Supply Voltage

High-Level Input Voltage

Low-Level Input Voltage

Input Clamp Current

High-Level Output Current

Low-Level Output Current

Pulse Width of Total Delay

Duty Cycle

Operating Free-Air Temperature

Package Dimensions

Min

4.75

2.0

Max

5.25

0.8

-18

-1.0

Unit

°C

.200

White Dot

Pin#1

PCA

EPA1145-4

Date Code

.300

.780 Max.

.250

Max.

.020

Typ.

.020

Min.

.010

Typ.

.365

Max.

.280

Max.

-55

+125

.100

*These two values are inter-dependent.

Input Pulse Test Conditions @ 25° C

EIN

TRI

PRR

VCC

Pulse Input Voltage

Pulse Width % of Total Delay

Pulse Rise Time (0.75 - 2.4 Volts)

Pulse Repetition Rate @ Td

≤

200 nS

Pulse Repetition Rate @ Td > 200 nS

Supply Voltage

3.2

110

2.0

1.0

100

5.0

Unit

Volts

MHz

KHz

Volts

.150 Typ.

DSA1145 Rev. A 2/5/96

QAF-CSO1 Rev. B 8/25/94

Unless Otherwise Noted Dimensions in Inches

Tolerances:

Fractional = ± 1/32

.XX = ± .030

.XXX = ± .010

ELECTRONICS

INC.

16799 SCHOENBORN ST.

NORTH HILLS, CA 91343

TEL: (818) 892-0761

FAX: (818) 894-5791

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