LC717A00AR
Capacitance‐Digital‐Converter
LSI for Electrostatic
Capacitive Touch Sensors
Overview
The LC717A00AR is a high-performance, low-cost capacitance-
digital-converter LSI for electrostatic capacitive touch sensor,
especially focused on usability. It has 8 channels capacitance-sensor
input. The built-in logic circuit can detect the state (ON/OFF) of each
input and output the result. This makes it ideal for various switch
applications.
The calibration function is automatically performed by the built-in
logic circuit during power activation or whenever there are
environmental changes. In addition, since initial settings of
parameters, such as gain, are configured, LC717A00AR can operate
as stand-alone when the recommended switch pattern is applied.
Also, since LC717A00AR has a serial interface compatible with
2
Ct and SPI bus, parameters can be adjusted using external devices
I
whenever necessary. Moreover, outputs of the 8-input capacitance
data can be detected and measured as 8-bit data.
Features
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VCT28
CASE 601AE
MARKING DIAGRAM
XXXXXXXX
YMDDD
•
Detection System: Differential Capacitance Detection
•
•
•
•
•
•
•
•
(Mutual Capacitance Type)
Input Capacitance Resolution: Can Detect Capacitance Changes in
the Femto Farad Order
Measurement Interval (8 Differential Inputs):
♦
18 ms (Typ) (at Initial Configuration)
♦
3 ms (Typ) (at Minimum Interval Configuration)
External Components for Measurement: Not Required
Current Consumption:
♦
320
mA
(Typ) (V
DD
= 2.8 V)
♦
740
mA
(Typ) (V
DD
= 5.5 V)
Supply Voltage: 2.6 V to 5.5 V
Detection Operations: Switch
Packages: VCT28
Interface: I
2
C Compatible Bus or SPI Selectable
XXXXX = Specific Device Code
Y = Year
M = Month
DDD = Additional Traceability Data
ORDERING INFORMATION
See detailed ordering and shipping information on page 11 of
this data sheet.
©
Semiconductor Components Industries, LLC, 2013
1
October, 2017 − Rev. 3
Publication Order Number:
LC717A00AR/D
LC717A00AR
Specifications
Table 1. ABSOLUTE MAXIMUM RATINGS
(T
A
= 25°C, V
SS
= 0 V)
Parameter
Supply Voltage
Input Voltage
Output Voltage
Power Dissipation
Peak Output Current
Total Output Current
Storage Temperature
Symbol
V
DD
V
IN
V
OUT
P
d max
I
OP
I
OA
T
stg
Ratings
−0.3 to +6.5
−0.3 to V
DD
+ 0.3
−0.3 to V
DD
+ 0.3
160
±8
±40
−55 to +125
Unit
V
V
V
mW
mA
mA
_C
(Note 1)
(Note 2)
T
A
= +105_C, Mounted on a substrate (Note 3)
Per terminal, 50% Duty ratio (Note 2)
Output total value of LSI, 25% Duty ratio
Remarks
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Apply to Cin0 to 7, Cref, nRST, SCL, SDA, SA, SCK, SI, nCS, GAIN.
2. Apply to Cdrv, Pout0 to 7, SDA, SO, ERROR, INTOUT.
3. 4-layer glass epoxy board (40
×
50
×
0.8t mm).
Table 2. RECOMMENDED OPERATING CONDITIONS
Parameter
Operating Supply Voltage
Supply Ripple + Noise
Operating Temperature
Symbol
V
DD
V
PP
T
opr
Conditions
Min
2.6
−
−40
Typ
−
−
25
Max
5.5
±20
105
Unit
V
mV
_C
(Note 4)
Remarks
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
4. Inserting a high-valued capacitor and a low-valued capacitor in parallel between V
DD
and V
SS
is recommended. In this case, the small-valued
capacitor should be at least 0.1
mF,
and is mounted near the LSI.
Table 3. ELECTRICAL CHARACTERISTICS
(V
SS
= 0 V, V
DD
= 2.6 to 5.5 V, T
A
= −40 to +105°C, Unless otherwise specified, the Cdrv drive frequency is f
CDRV
= 143 kHz.
Not tested at low temperature before shipment.)
Parameter
Capacitance Detection Resolution
Output Noise RMS
Input Offset Capacitance
Adjustment Range
Input Offset Capacitance
Adjustment Resolution
Cin Offset Drift
Cin Detection Sensitivity
Cin Pin Leak Current
Cin Allowable Parasitic Input
Capacitance
Cdrv Drive Frequency
Cdrv Pin Leak Current
nRST Minimum Pulse Width
Power-on Reset Time
Power-on Reset Operation
Condition: Hold Time
Power-on Reset Operation
Condition: Input Voltage
Symbol
N
N
RMS
Coff
RANGE
Coff
RESO
Cin
DRIFT
Cin
SENSE
I
Cin
Cin
SUB
f
CDRV
I
CDRV
t
NRST
t
POR
t
POROP
V
POROP
Cdrv = Hi−Z
Minimum gain setting
Minimum gain setting
Cin = Hi−Z
Cin against V
SS
Minimum gain setting
Conditions
Min
−
−
−
−
−
0.04
−
−
100
−
1
−
10
−
Typ
−
−
±8.0
8
−
−
±25
−
143
±25
−
−
−
−
Max
8
±1.0
−
−
±8
0.12
±500
30
186
±500
−
20
−
0.1
Unit
bit
LSB
pF
bit
LSB
LSB/fF
nA
pF
kHz
nA
ms
ms
ms
V
(Note 5)
(Note 5)
(Notes 5, 7)
(Note 5)
(Note 6)
(Notes 5, 7)
(Notes 5, 7)
Remarks
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LC717A00AR
Table 3. ELECTRICAL CHARACTERISTICS
(continued)
(V
SS
= 0 V, V
DD
= 2.6 to 5.5 V, T
A
= −40 to +105°C, Unless otherwise specified, the Cdrv drive frequency is f
CDRV
= 143 kHz.
Not tested at low temperature before shipment.)
Parameter
Power-on Reset Operation
Condition: Power Supply Rise Rate
Pin Input Voltage
Symbol
t
VDD
V
IH
V
IL
Pin Output Voltage
V
OH
V
OL
SDA Pin Output Voltage
Pin Leak Current
Current Consumption
V
OL I2C
I
LEAK
I
DD
When stand-alone
configuration and
non-touch
V
DD
= 2.8 V
When stand-alone
configuration and
non-touch
V
DD
= 5.5 V
I
STBY
During Sleep process
Conditions
0 V to V
DD
High input
Low input
High output
(I
OH
= +3 mA)
Low output
(I
OL
= −3 mA)
SDA Low output
(I
OL
= −3 mA)
Min
1
0.8 V
DD
−
0.8 V
DD
−
−
−
−
Typ
−
−
−
−
−
−
−
320
Max
−
−
0.2 V
DD
−
0.2 V
DD
0.4
±1
390
V
mA
mA
(Note 10)
(Notes 5, 7)
V
(Note 9)
Unit
V/ms
V
Remarks
(Note 5)
(Notes 5, 8)
−
740
900
−
−
1
mA
(Note 7)
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. Design-guaranteed values (not tested before shipment).
6. Measurements conducted using the test mode in the LSI.
7. T
A
= +25_C.
8. Apply to nRST, SCL, SDA, SA, SCK, SI, nCS, GAIN.
9. Apply to Cdrv, Pout0 to 7, SO, ERROR, INTOUT.
10. Apply to nRST, SCL, SDA, SA, SCK, SI, nCS, GAIN.
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LC717A00AR
Table 4. I
2
C COMPATIBLE BUS TIMING CHARACTERISTICS
(V
SS
= 0 V, V
DD
= 2.6 to 5.5 V, T
A
= −40 to +105°C, Not tested at low temperature before shipment.)
Parameter
SCL Clock Frequency
START Condition Hold Time
SCL Clock Low Period
SCL Clock High Period
Repeated START Condition
Setup Time
Data Hold Time
Data Setup Time
SDA, SCL Rise/Fall Time
STOP Condition Setup Time
STOP-to-START Bus Release Time
Symbol
f
SCL
t
HD;STA
t
LOW
t
HIGH
t
SU;STA
t
HD;DAT
t
SU;DAT
t
r
/ t
f
t
SU;STO
t
BUF
Pin Name
SCL
SCL, SDA
SCL
SCL
SCL, SDA
SCL, SDA
SCL, SDA
SCL, SDA
SCL, SDA
SCL, SDA
Conditions
Min
−
0.6
1.3
0.6
0.6
0
100
−
0.6
1.3
Typ
−
−
−
−
−
−
−
−
−
−
Max
400
−
−
−
−
0.9
−
300
−
−
Unit
kHz
ms
ms
ms
ms
ms
ns
ns
ms
ms
(Note 11)
(Note 11)
(Note 11)
(Note 11)
Remarks
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
11. Design-guaranteed values (not tested before shipment).
Table 5. SPI BUS TIMING CHARACTERISTICS
(V
SS
= 0 V, V
DD
= 2.6 to 5.5 V, T
A
= −40 to +105°C, Not tested at low temperature before shipment.)
Parameter
SCK Clock Frequency
SCK Clock Low Time
SCK Clock High Time
Input Signal Rise/Fall Time
nCS Setup Time
SCK Clock Setup Time
Data Setup Time
Data Hold Time
nCS Hold Time
SCK Clock Hold Time
nCS Standby Pulse Width
Output High Impedance Time
from nCS
Output Data Determination Time
Output Data Hold Time
Output Low Impedance Time
from SCK Clock
Symbol
f
SCK
t
LOW
t
HIGH
t
r
/ t
f
t
SU;NCS
t
SU;SCK
t
SU;SI
t
HD;SI
t
HD;NCS
t
HD;SCK
t
CPH
t
CHZ
t
v
t
HD;SO
t
CLZ
Pin Name
SCK
SCK
SCK
nCS, SCK, SI
nCS, SCK
nCS, SCK
SCK, SI
SCK, SI
nCS, SCK
nCS, SCK
nCS
nCS, SO
SCK, SO
SCK, SO
SCK, SO
Conditions
Min
−
90
90
−
90
90
20
30
90
90
90
−
−
0
0
Typ
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
Max
5
−
−
300
−
−
−
−
−
−
−
80
80
−
−
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(Note 12)
(Note 12)
(Note 12)
(Note 12)
(Note 12)
(Note 12)
(Note 12)
(Note 12)
(Note 12)
(Note 12)
(Note 12)
(Note 12)
(Note 12)
(Note 12)
Remarks
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
12. Design-guaranteed values (not tested before shipment).
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LC717A00AR
Power-On Reset (POR)
When power is turned on, power-on reset is enabled inside
the LSI and its state is released after a certain power-on reset
time, t
POR.
Power-on reset operation condition: Power
supply rise rate t
VDD
must be at least 1 V/ms.
Since INTOUT pin changes from “High” to “Low” at the
same time as the released of power-on reset state, it is
possible to verify the t
POR
externally.
During power-on reset state, Cin, Cref and Pout are
unknown.
V
DD
tVDD
tPOR
VPOROP
tPOROP
tPOR
POR
(LSI Internal
Signal)
RESET
RELEASE
UNKNOWN
RESET
RELEASE
INTOUT
VALID
UNKNOWN
Cin,
Cref,
Pout
UNKNOWN
VALID
UNKNOWN
Figure 1.
I
2
C Compatible Bus Data Timing
90%
90%
10%
tSU;STA
90%
10% 10%
tHD;STA
tHIGH
10%
10%
tHD;STA
90%
90%
10%
tSU;STO
90%
tBUF
90%
10%
SDA
10%
tLOW
90%
tHD;DAT
90% 90%
10%
tSU;DAT
SCL
tr
tf
Repeated START
condition
STOP
condition
START
condition
START
condition
Figure 2.
I
2
C Compatible Bus Communication Formats
•
Write format (data can be written into sequentially incremented addresses)
START
Slave Address
Write=L
ACK
Register Address (N)
ACK
Data written to Register Address (N)
ACK
Data written to Register Address (N+1) ACK
STOP
Slave
Slave
Slave
Slave
Figure 3.
•
Read format (data can be read from sequentially incremented addresses)
START
Slave Address
Write=L
ACK
Register Address (N)
ACK
Slave
RESTART
Slave Address
Read=H ACK
Data read from Register Address (N)
Slave
ACK
Data read from Register Address (N+1)
ACK Data read from Register Address (N+2) NACK STOP
Slave
Master
Master
Master
Figure 4.
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