Data Sheet
FEATURES
Throughput rate: 625 kSPS
Specified for V
DD
of 2.7 V to 5.25 V
Power consumption
3.6 mW maximum at 625 kSPS with 3 V supplies
7.5 mW maximum at 625 kSPS with 5 V supplies
8 analog input channels with a sequencer
Software-configurable analog inputs
8-channel single-ended inputs
4-channel fully differential inputs
4-channel pseudo differential inputs
7-channel pseudo differential inputs
Accurate on-chip 2.5 V reference
±0.2% maximum @ 25°C, 25 ppm/°C maximum
69 dB SINAD at 50 kHz input frequency
No pipeline delays
High speed parallel interface with word/byte modes
Full shutdown mode: 2 μA maximum
32-lead LFCSP and TQFP packages
8-Channel, 625 kSPS, 12-Bit
Parallel ADCs with a Sequencer
AD7938-6
FUNCTIONAL BLOCK DIAGRAM
V
DD
V
REFIN
/
V
REFOUT
2.5V
V
REF
I/P
MUX
V
IN
7
12-BIT
SAR ADC
AND
CONTROL
CLKIN
CONVST
BUSY
AGND
AD7938-6
V
IN
0
T/H
SEQUENCER
PARALLEL INTERFACE/CONTROL REGISTER
V
DRIVE
DB0 DB11
CS RD WR W/B
DGND
Figure 1.
GENERAL DESCRIPTION
The AD7938-6 is a 12-bit, high speed, low power, successive
approximation (SAR) analog-to-digital converter (ADC). The
part operates from a single 2.7 V to 5.25 V power supply and
features throughput rates up to 625 kSPS. The part contains a
low noise, wide bandwidth, differential track-and-hold
amplifier that can handle input frequencies up to 50 MHz.
The AD7938-6 features eight analog input channels with a
channel sequencer that allows a preprogrammed selection of
channels to be converted sequentially. The part can operate
with either single-ended, fully differential, or pseudo differential
analog inputs.
The conversion process and data acquisition are controlled
using standard control inputs that allow easy interfacing with
microprocessors and DSPs. The input signal is sampled on the
falling edge of CONVST and the conversion is initiated at
this point.
The AD7938-6 has an accurate on-chip 2.5 V reference that
can be used as the reference source for the analog-to-digital
conversion. Alternatively, this pin can be overdriven to provide
an external reference.
The AD7938-6 uses advanced design techniques to achieve very
low power dissipation at high throughput rates. The part also
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
features flexible power management options. An on-chip
control register allows the user to set up different operating
conditions, including analog input range and configuration,
output coding, power management, and channel sequencing.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
High throughput with low power consumption.
Eight analog inputs with a channel sequencer.
Accurate on-chip 2.5 V reference.
Single-ended, pseudo differential, or fully differential
analog inputs that are software selectable.
Single-supply operation with V
DRIVE
function. The V
DRIVE
function allows the parallel interface to connect directly to
3 V or 5 V processor systems independent of V
DD
.
No pipeline delay.
Accurate control of the sampling instant via a CONVST
input and once-off conversion control.
6.
7.
Table 1.
Similar Device
AD7938/AD7939
AD7933/AD7934
AD7934-6
No. of Bits
12/10
10/12
12
No. of Channels
8
4
4
Speed
1.5 MSPS
1.5 MSPS
625 kSPS
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2004–2011 Analog Devices, Inc. All rights reserved.
04751-001
AD7938-6
TABLE OF CONTENTS
Features .............................................................................................. 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ....................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications .................................................................. 5
Absolute Maximum Ratings............................................................ 6
ESD Caution .................................................................................. 6
Pin Configuration and Function Descriptions ............................. 7
Typical Performance Characteristics ............................................. 9
Terminology .................................................................................... 11
On-Chip Registers .......................................................................... 13
Control Register .......................................................................... 13
Sequencer Operation ................................................................. 14
Shadow Register.......................................................................... 14
Circuit Information ........................................................................ 16
Data Sheet
Converter Operation.................................................................. 16
ADC Transfer Function ............................................................. 16
Typical Connection Diagram ................................................... 17
Analog Input Structure .............................................................. 17
Analog Inputs ............................................................................. 18
Analog Input Selection .............................................................. 20
Reference ..................................................................................... 21
Parallel Interface ......................................................................... 23
Power Modes of Operation ....................................................... 26
Power vs. Throughput Rate ....................................................... 27
Microprocessor Interfacing ....................................................... 27
Application Hints ........................................................................... 29
Grounding and Layout .............................................................. 29
PCB Design Guidelines for Chip Scale Package .................... 29
Evaluating the AD7938-6 Performance .................................. 29
Outline Dimensions ....................................................................... 30
Ordering Guide .......................................................................... 31
REVISION HISTORY
10/11—Rev. B to Rev. C
Change to Features Section ............................................................. 1
10/11—Rev. A to Rev. B
Changes to Table 2 ............................................................................ 3
Changes to Figure 2 and Table 5 ..................................................... 7
Added Exposed Pad Notation to Outline Dimensions ............. 30
Changes to Ordering Guide .......................................................... 31
2/07—Rev. 0 to Rev. A
Changes to Specifications ................................................................ 3
Changes to Figure 13 ...................................................................... 10
Changes to Sequencer Operation Section ................................... 14
Changes to Analog Inputs Section ............................................... 18
Updated Outline Dimensions ....................................................... 30
10/04—Revision 0: Initial Version
Rev. C | Page 2 of 32
Data Sheet
SPECIFICATIONS
AD7938-6
V
DD
= V
DRIVE
= 2.7 V to 5.25 V, internal/external V
REF
= 2.5 V, unless otherwise noted; f
CLKIN
= 10 MHz, f
SAMPLE
= 625 kSPS; T
A
= T
MIN
to
T
MAX1
, unless otherwise noted.
Table 2.
Parameter
DYNAMIC PERFORMANCE
Signal-to-Noise + Distortion (SINAD)
2
Signal-to-Noise Ratio (SNR)
2
Total Harmonic Distortion (THD)
2
Peak Harmonic or Spurious Noise (SFDR)
2
Intermodulation Distortion (IMD)
2
Second-Order Terms
Third-Order Terms
Channel-to-Channel Isolation
Aperture Delay
2
Aperture Jitter
2
Full Power Bandwidth
2
DC ACCURACY
Resolution
Integral Nonlinearity
2
Differential Nonlinearity
2
Differential Mode
Single-Ended Mode
Single-Ended and Pseudo Differential Input
Offset Error
2
Offset Error Match
2
Gain Error
2
Gain Error Match
2
Fully Differential Input
Positive Gain Error
2
Positive Gain Error Match
2
Zero-Code Error
2
Zero-Code Error Match
2
Negative Gain Error
2
Negative Gain Error Match
2
ANALOG INPUT
Single-Ended Input Range
Pseudo Differential Input Range:
V
IN+
V
IN−
Fully Differential Input Range
V
IN+
and V
IN−
V
IN+
and V
IN−
Value
1
69
67
71
69
−73
−69.5
−72
−86
−90
−85
5
72
50
10
12
±1
±1.5
±0.95
−0.95/+1.5
±12
±3
±3
±2
±3
±1.5
±9.5
±1
±3
±1.5
0 to V
REF
0 to 2 × V
REF
0 to V
REF
0 to 2 × V
REF
−0.3 to +0.7
−0.3 to +1.8
V
CM
± V
REF
/2
V
CM
± V
REF
Unit
dB min
dB min
dB min
dB min
dB max
dB max
dB max
dB typ
dB typ
dB typ
ns typ
ps typ
MHz typ
MHz typ
Bits
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
Twos complement output coding
LSB max
LSB typ
LSB max
LSB typ
LSB max
LSB typ
V
V
V
V
V typ
V typ
V
V
RANGE bit = 0
RANGE bit = 1
RANGE bit = 0
RANGE bit = 1
V
DD
= 3 V
V
DD
= 5 V
V
CM
= common-mode voltage
3
= V
REF
/2
V
CM
= V
REF
, V
IN+
or V
IN−
must remain within GND/V
DD
Test Conditions/Comments
f
IN
= 50 kHz sine wave
Differential mode
Single-ended mode
Differential mode
Single-ended mode
−85 dB typ, differential mode
−80 dB typ, single-ended mode
−82 dB typ
fa = 30 kHz, fb = 50 kHz
f
IN
= 50 kHz, f
NOISE
= 300 kHz
@ 3 dB
@ 0.1 dB
Differential mode
Single-ended mode
Guaranteed no missed codes to 12 bits
Guaranteed no missed codes to 12 bits
Straight binary output coding
Rev. C | Page 3 of 32
AD7938-6
Parameter
DC Leakage Current
4
Input Capacitance
REFERENCE INPUT/OUTPUT
V
REF
Input Voltage
5
DC Leakage Current
V
REFOUT
Output Voltage
V
REFOUT
Temperature Coefficient
V
REF
Noise
V
REF
Output Impedance
V
REF
Input Capacitance
LOGIC INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
IN
Input Capacitance, C
IN
4
LOGIC OUTPUTS
Output High Voltage, V
OH
Output Low Voltage, V
OL
Floating-State Leakage Current
Floating-State Output Capacitance
4
Output Coding
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time
Throughput Rate
POWER REQUIREMENTS
V
DD
V
DRIVE
I
DD 6
Normal Mode (Static)
Normal Mode (Operational)
Autostandby Mode
Full/Autoshutdown Mode (Static)
Power Dissipation
Normal Mode (Operational)
Autostandby Mode (Static)
Full/Autoshutdown Mode (Static)
Value
1
±1
45
10
2.5
±1
2.5
25
5
10
130
10
15
25
2.4
0.8
±5
10
2.4
0.4
±3
10
Straight (Natural) Binary
Twos Complement
t
2
+ 13 t
CLKIN
125
80
625
2.7/5.25
2.7/5.25
0.8
1.5
1.2
0.3
160
2
7.5
3.6
800
480
10
6
Unit
μA max
pF typ
pF typ
V
μA max
V
ppm/°C max
ppm/°C typ
μV typ
μV typ
Ω typ
pF typ
pF typ
V min
V max
μA max
pF max
V min
V max
μA max
pF max
Test Conditions/Comments
When in track
When in hold
±1% for specified performance
±0.2% max @ 25°C
Data Sheet
0.1 Hz to 10 Hz bandwidth
0.1 Hz to 1 MHz bandwidth
When in track
When in hold
Typically 10 nA, V
IN
= 0 V or V
DRIVE
I
SOURCE
= 200 μA
I
SINK
= 200 μA
CODING bit = 0
CODING bit = 1
ns
ns max
ns typ
kSPS max
V min/max
V min/max
mA typ
mA max
mA max
mA typ
μA typ
μA max
mW max
mW max
μW typ
μW typ
μW max
μW max
Digital inputs = 0 V or V
DRIVE
V
DD
= 2.7 V to 5.25 V, SCLK on or off
V
DD
= 4.75 V to 5.25 V
V
DD
= 2.7 V to 3.6 V
f
SAMPLE
= 100 kSPS, V
DD
= 5 V
Static
SCLK on or off
V
DD
= 5 V
V
DD
= 3 V
V
DD
= 5 V
V
DD
= 3 V
V
DD
= 5 V
V
DD
= 3 V
Full-scale step input
Sine wave input
1
2
Temperature range is −40°C to +85°C.
See the Terminology section.
3
For full common-mode range, see Figure 25 and Figure 26.
4
Sample tested during initial release to ensure compliance.
5
This device is operational with an external reference in the range of 0.1 V to V
DD
. See the Reference section for more information.
6
Measured with a midscale dc analog input.
Rev. C | Page 4 of 32
Data Sheet
TIMING SPECIFICATIONS
AD7938-6
V
DD
= V
DRIVE
= 2.7 V to 5.25 V, internal/external V
REF
= 2.5 V, unless otherwise noted; f
CLKIN
= 10MHz, f
SAMPLE
= 625 kSPS; T
A
= T
MIN
to
T
MAX
, unless otherwise noted.
Table 3.
Parameter
1
f
CLKIN 2
Limit at T
MIN
, T
MAX
700
10
30
10
15
50
0
0
10
10
10
10
0
0
30
30
3
50
0
0
10
0
10
40
15.7
7.8
Unit
kHz min
MHz
max
ns min
ns min
ns min
ns max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns max
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns min
Description
CLKIN frequency
t
QUIET
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
t
12
t
13 3
t
14 4
t
15
t
16
t
17
t
18
t
19
t
20
t
21
t
22
1
Minimum time between end of read and start of next conversion, that is, time from when
the data bus goes into three-state until the next falling edge of CONVST.
CONVST pulse width.
CONVST falling edge to CLKIN falling edge setup time.
CLKIN falling edge to BUSY rising edge.
CS to WR setup time.
CS to WR hold time.
WR pulse width.
Data setup time before WR.
Data hold after WR.
New data valid before falling edge of BUSY.
CS to RD setup time.
CS to RD hold time.
RD pulse width.
Data access time after RD.
Bus relinquish time after RD.
Bus relinquish time after RD.
HBEN to RD setup time.
HBEN to RD hold time.
Minimum time between reads/writes.
HBEN to WR setup time.
HBEN to WR hold time.
CLKIN falling edge to BUSY falling edge.
CLKIN low pulse width.
CLKIN high pulse width.
Sample tested during initial release to ensure compliance. All input signals are specified with t
RISE
= t
FALL
= 5 ns (10% to 90% of V
DD
) and timed from a voltage level of
1.6 V. All timing specifications given above are with a 25 pF load capacitance (see Figure 35, Figure 36, Figure 37, and Figure 38).
2
Minimum CLKIN for specified performance, with slower CLKIN frequencies performance specifications apply typically.
3
The time required for the output to cross 0.4 V or 2.4 V.
4
t
14
is derived from the measured time taken by the data outputs to change 0.5 V. The measured number is then extrapolated back to remove the effects of charging or
discharging the 25 pF capacitor. This means that the time, t
14
, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the
bus loading.
Rev. C | Page 5 of 32
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