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5962-9560015QXA

Description
Standard SRAM, 512KX8, 12ns, CMOS, CDIP32, 0.600 INCH, CERAMIC, DIP-32
Categorystorage    storage   
File Size1MB,41 Pages
ManufacturerMicrosemi
Websitehttps://www.microsemi.com
Download Datasheet Parametric View All

5962-9560015QXA Overview

Standard SRAM, 512KX8, 12ns, CMOS, CDIP32, 0.600 INCH, CERAMIC, DIP-32

5962-9560015QXA Parametric

Parameter NameAttribute value
Objectid1198216682
package instructionDIP,
Reach Compliance Codecompliant
ECCN code3A001.A.2.C
Maximum access time12 ns
JESD-30 codeR-CDIP-T32
JESD-609 codee0
memory density4194304 bit
Memory IC TypeSTANDARD SRAM
memory width8
Number of functions1
Number of terminals32
word count524288 words
character code512000
Operating modeASYNCHRONOUS
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
organize512KX8
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeDIP
Package shapeRECTANGULAR
Package formIN-LINE
Parallel/SerialPARALLEL
Certification statusNot Qualified
Filter levelMIL-PRF-38535 Class Q
Maximum seat height7.493 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelMILITARY
Terminal surfaceTIN LEAD
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
width15.24 mm
REVISIONS
LTR
C
DESCRIPTION
Change minimum dimensions A, b, and E for case outline U. Add
CAGE 65786 as a source of supply. Editorial changes throughout. -
ksr
Change case outline 9, dimension A from .114 inches to .130 inches. -
glg
Added low-power devices 09 - 14 to drawing. Removed CAGE
0EU86 for devices 05 - 08. - glg
Changed minimum dimension b for package "U" from 0.015 inches to
0.012 inches. - glg
Changed minimum dimension b for package "M" from 0.019 inches to
0.012 inches. Updated boilerplate paragraphs. ksr
Table I; Changed the I
OL
from 8 mA to 6 mA V
OL
test. Added device
types 15 and 16. Editorial changes throughout. -sld
Add case outline 7. Add CAGE 0EU86 as source of supply for case
outline 7. Editorial changes throughout. tcr
Add device 17 and add case outline 6. Add CAGE 6S055 as source
of supply for case outline 6. Some editorial changes. ksr
Update drawing to meet current MIL-PRF-38535 requirements. - glg
DATE
97-10-24
APPROVED
Raymond Monnin
D
E
F
G
H
J
K
L
00-03-01
00-11-22
00-12-13
02-02-12
04-05-25
08-08-18
09-01-22
16-09-01
Raymond Monnin
Raymond Monnin
Raymond Monnin
Raymond Monnin
Raymond Monnin
Robert M. Heber
Robert M. Heber
Charles Saffle
REV
SHEET
REV
SHEET
REV STATUS
OF SHEETS
PMIC N/A
L
15
L
16
L
17
L
18
REV
SHEET
PREPARED BY
Jeff Bowling
L
19
L
20
L
21
L
1
L
22
L
2
L
23
L
3
L
24
L
4
L
25
L
5
L
26
L
6
L
27
L
7
L
28
L
8
L
29
L
9
L
30
L
10
L
31
L
11
L
32
L
12
L
13
L
14
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
http://www.landandmaritime.dla.mil/
STANDARD
MICROCIRCUIT
DRAWING
THIS DRAWING IS
AVAILABLE
FOR USE BY All
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
AMSC N/A
CHECKED BY
Jeff Bowling
APPROVED BY
Michael. A. Frye
DRAWING APPROVAL DATE
96-03-05
REVISION LEVEL
L
MICROCIRCUITS, MEMORY, DIGITAL,
CMOS, 512K X 8 STATIC RANDOM
ACCESS MEMORY (SRAM),
MONOLITHIC SILICON
SIZE
A
SHEET
1 OF
32
5962-E505-16
CAGE CODE
67268
5962-95600
DSCC FORM 2233
APR 97
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