Changes to Endnote 3 ...................................................................... 4
Changes to Pin Configuration Section .......................................... 8
Changes to Evaluating the AD7679’s Performance Section...... 25
Changes to Ordering Guide .......................................................... 26
7/03—Revision 0: Initial Version
Rev. A | Page 2 of 28
AD7674
SPECIFICATIONS
Table 2. –40°C to +85°C, V
REF
= 4.096 V, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.
Parameter
RESOLUTION
ANALOG INPUT
Voltage Range
Operating Input Voltage
Analog Input CMRR
Input Current
Input Impedance
1
THROUGHPUT SPEED
Complete Cycle
Throughput Rate
Time between Conversions
Complete Cycle
Throughput Rate
Complete Cycle
Throughput Rate
DC ACCURACY
Integral Linearity Error
Differential Linearity Error
No Missing Codes
Transition Noise
Zero Error, T
MIN
to T
MAX
Zero Error, T
MIN
to T
MAX
Zero Error Temperature Drift
Gain Error, T
MIN
to T
MAX3
Gain Error, T
MIN
to T
MAX3
Gain Error Temperature Drift
Power Supply Sensitivity
AC ACCURACY
Signal-to-Noise
Conditions
Min
18
–V
REF
–0.1
65
100
Typ
Max
Unit
Bits
V
V
dB
μA
V
IN+
– V
IN–
V
IN+
, V
IN–
to AGND
f
IN
= 100 kHz
800 kSPS throughput
+V
REF
AVDD
In warp mode
In warp mode
In warp mode
In normal mode
In normal mode
In impulse mode
In impulse mode
1
0
0
–2.5
–1
18
1.25
800
1
1.5
666
1.75
570
+2.5
+1.75
0.7
μs
kSPS
ms
μs
kSPS
μs
kSPS
LSB
2
LSB
Bits
LSB
LSB
LSB
ppm/°C
% of FSR
% of FSR
ppm/°C
LSB
dB
4
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
MHz
ns
ps rms
ns
ns
V
REF
= 5 V
In warp mode
In normal or impulse mode
All modes
In warp mode
In normal or impulse mode
All modes
AVDD = 5 V ± 5%
f
IN
= 2 kHz, V
REF
= 5 V
V
REF
= 4.096 V
f
IN
= 10 kHz, V
REF
= 4.096 V
f
IN
= 100 kHz, V
REF
= 4.096 V
V
IN+
= V
IN–
= V
REF
/2 = 2.5 V
f
IN
= 2 kHz
f
IN
= 10 kHz
f
IN
= 100 kHz
f
IN
= 2 kHz
f
IN
= 10 kHz
f
IN
= 100 kHz
f
IN
= 2 kHz, V
REF
= 4.096 V
f
IN
= 2 kHz, –60 dB input
–25
–85
±0.5
–0.034
–0.048
±1.6
±4
101
99
98
97
103
120
118
105
–115
–113
–98
98
40
26
2
5
+25
+85
+0.034
+0.048
97.5
Dynamic Range
Spurious-Free Dynamic Range
Total Harmonic Distortion
Signal-to-(Noise + Distortion)
–3 dB Input Bandwidth
SAMPLING DYNAMICS
Aperture Delay
Aperture Jitter
Transient Response
Overvoltage Recovery
Full-scale step
250
250
Rev. A | Page 3 of 28
AD7674
Parameter
REFERENCE
External Reference Voltage Range
REF Voltage with Reference Buffer
Reference Buffer Input Voltage Range
REFBUFIN Input Current
REF Current Drain
DIGITAL INPUTS
Logic Levels
V
IL
V
IH
I
IL
I
IH
DIGITAL OUTPUTS
Data Format
5
Pipeline Delay
6
V
OL
V
OH
POWER SUPPLIES
Specified Performance
AVDD
DVDD
OVDD
Operating Current
8
AVDD
DVDD
9
OVDD
9
POWER DISSIPATION
9
Conditions
REF
REFBUFIN = 2.5 V
REFBUFIN
800 kSPS throughput
Min
3
4.05
1.8
–1
Typ
4.096
4.096
2.5
330
Max
AVDD + 0.1
4.15
2.6
+1
Unit
V
V
V
μA
μA
–0.3
+2.0
–1
–1
+0.8
DVDD + 0.3
+1
+1
V
V
μA
μA
I
SINK
= 1.6 mA
I
SOURCE
= –500 μA
0.4
OVDD – 0.6
V
V
4.75
4.75
2.7
800 kSPS throughput
5
5
5.25
5.25
DVDD + 0.3
7
V
V
V
mA
mA
μA
mW
μW
mW
mW
°C
PDBUF high @ 500 kSPS
10
PDBUF high @ 1 kSPS
10
PDBUF high @ 800 kSPS
8
PDBUF low @ 800 kSPS
8
T
MIN
to T
MAX
–40
16
6.5
50
78
160
114
126
90
126
138
+85
TEMPERATURE RANGE
11
Specified Performance
1
2
See Analog Inputs section.
LSB means Least Significant Bit. With the ±4.096 V input range, 1 LSB is 31.25 μV.
3
See Definitions of Specifications section. The nominal gain error is not centered at zero and is −0.029% of FSR. This specification is the deviation from this nominal
value. These specifications do not include the error contribution from the external reference, but do include the error contribution from the reference buffer if used.
4
All specifications in dB are referred to a full-scale input, FS. Tested with an input signal at 0.5 dB below full scale unless otherwise specified.
5
Data Format Parallel or Serial 18-Bit.
6
Conversion results are available immediately after completed conversion.
7
The max should be the minimum of 5.25 V and DVDD + 0.3 V.
8
In Warp mode.
9
Tested in Parallel Reading mode.
10
In Impulse mode.
11
Contact factory for extended temperature range.
Rev. A | Page 4 of 28
AD7674
TIMING SPECIFICATIONS
Table 3. –40°C to +85°C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.
Parameter
Refer to Figure 34 and Figure 35
Convert Pulsewidth
Time between Conversions (Warp Mode/Normal Mode/Impulse Mode)
1
CNVST LOW to BUSY HIGH Delay
BUSY HIGH All Modes Except Master Serial Read after Convert
(Warp Mode/Normal Mode/Impulse Mode)
Aperture Delay
End of Conversion to BUSY LOW Delay
Conversion Time (Warp Mode/Normal Mode/Impulse Mode)
Acquisition Time
RESET Pulsewidth
Refer to Figure 36, Figure 37, and Figure 38 (Parallel Interface Modes)
CNVST LOW to Data Valid Delay (Warp Mode/Normal Mode/Impulse Mode)
Data Valid to BUSY LOW Delay
Bus Access Request to Data Valid
Bus Relinquish Time
Refer to Figure 40 and Figure 41 (Master Serial Interface Modes)
2
CS LOW to SYNC Valid Delay
CS LOW to Internal SCLK Valid Delay
CS LOW to SDOUT Delay
CNVST LOW to SYNC Delay (Warp Mode/Normal Mode/Impulse Mode)
SYNC Asserted to SCLK First Edge Delay
3
Internal SCLK Period
3
Internal SCLK HIGH
3
Internal SCLK LOW
3
SDOUT Valid Setup Time
3
SDOUT Valid Hold Time
3
SCLK Last Edge to SYNC Delay
3
CS HIGH to SYNC HI-Z
CS HIGH to Internal SCLK HI-Z
CS HIGH to SDOUT HI-Z
BUSY HIGH in Master Serial Read after Convert
3
CNVST LOW to SYNC Asserted Delay
(Warp Mode/Normal Mode/Impulse Mode)
SYNC Deasserted to BUSY LOW Delay
Refer to Figure 42 and Figure 43 (Slave Serial Interface Modes)
External SCLK Setup Time
External SCLK Active Edge to SDOUT Delay
SDIN Setup Time
SDIN Hold Time
External SCLK Period
External SCLK HIGH
External SCLK LOW
1
2
Symbol
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
t
12
t
13
t
14
t
15
t
16
t
17
t
18
t
19
t
20
t
21
t
22
t
23
t
24
t
25
t
26
t
27
t
28
t
29
t
30
t
31
t
32
t
33
t
34
t
35
t
36
t
37
Min
10
1.25/1.5/1.75
Typ
Max
Unit
ns
μs
ns
μs
ns
ns
μs
ns
ns
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
35
1/1.25/1.5
2
10
1/1.25/1.5
250
10
1/1.25/1.5
20
5
45
15
10
10
10
25/275/525
3
25
12
7
4
2
3
40
10
10
10
Table 4
1/1.25/1.5
25
5
3
5
5
25
10
10
μs
ns
ns
ns
ns
ns
ns
ns
ns
18
In Warp mode only, the maximum time between conversions is 1 ms; otherwise, there is no required maximum time.
In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C
L
of 10 pF; otherwise, the load is 60 pF maximum.
3
In Serial Master Read during Convert mode. See Table 4 for Serial Master Read after Convert mode.
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Test/Measurement
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