Features
•
Incorporates the ARM920T
™
ARM
®
Thumb
®
Processor
200 MIPS at 180 MHz, Memory Management Unit
16-KByte Data Cache, 16-KByte Instruction Cache, Write Buffer
In-circuit Emulator including Debug Communication Channel
Mid-level Implementation Embedded Trace Macrocell
™
(256-ball BGA Package
only)
Low Power: On VDDCORE 24.4 mA in Normal Mode, 520 µA in Standby Mode
Additional Embedded Memories
– 16K Bytes of SRAM and 128K Bytes of ROM
External Bus Interface (EBI)
– Supports SDRAM, Static Memory, Burst Flash, Glueless Connection to
CompactFlash
®
and NAND Flash/SmartMedia
®
System Peripherals for Enhanced Performance:
– Enhanced Clock Generator and Power Management Controller
– Two On-chip Oscillators with Two PLLs
– Very Slow Clock Operating Mode and Software Power Optimization Capabilities
– Four Programmable External Clock Signals
– System Timer Including Periodic Interrupt, Watchdog and Second Counter
– Real-time Clock with Alarm Interrupt
– Debug Unit, Two-wire UART and Support for Debug Communication Channel
– Advanced Interrupt Controller with 8-level Priority, Individually Maskable Vectored
Interrupt Sources, Spurious Interrupt Protected
– Seven External Interrupt Sources and One Fast Interrupt Source
– Four 32-bit PIO Controllers with Up to 122 Programmable I/O Lines, Input Change
Interrupt and Open-drain Capability on Each Line
– 20-channel Peripheral DMA Controller (PDC)
Ethernet MAC 10/100 Base-T
– Media Independent Interface (MII) or Reduced Media Independent Interface (RMII)
– Integrated 28-byte FIFOs and Dedicated DMA Channels for Receive and Transmit
USB 2.0 Full Speed (12 Mbits per second) Host Double Port
– Dual On-chip Transceivers (Single Port Only on 208-lead PQFP Package)
– Integrated FIFOs and Dedicated DMA Channels
USB 2.0 Full Speed (12 Mbits per second) Device Port
– On-chip Transceiver, 2-Kbyte Configurable Integrated FIFOs
Multimedia Card Interface (MCI)
– Automatic Protocol Control and Fast Automatic Data Transfers
– MMC and SD Memory Card-compliant, Supports Up to Two SD Memory Cards
Three Synchronous Serial Controllers (SSC)
– Independent Clock and Frame Sync Signals for Each Receiver and Transmitter
– I
2
S Analog Interface Support, Time Division Multiplex Support
– High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer
Four Universal Synchronous/Asynchronous Receiver/Transmitters (USART)
– Support for ISO7816 T0/T1 Smart Card
– Hardware Handshaking
– RS485 Support, IrDA
®
Up To 115 Kbps
– Full Modem Control Lines on USART1
Master/Slave Serial Peripheral Interface (SPI)
– 8- to 16-bit Programmable Data Length, 4 External Peripheral Chip Selects
–
–
–
–
•
•
•
ARM920T-based
Microcontroller
AT91RM9200
•
•
•
•
•
•
•
•
Rev. 1768I-ATARM–09-Jul-09
•
Two 3-channel, 16-bit Timer/Counters (TC)
– Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel
– Double PWM Generation, Capture/Waveform Mode, Up/Down Capability
Two-wire Interface (TWI)
– Master Mode Support, All 2-wire Atmel EEPROMs Supported
IEEE
®
1149.1 JTAG Boundary Scan on All Digital Pins
Power Supplies
– 1.65V to 1.95V for VDDCORE, VDDOSC and VDDPLL
– 3.0V to 3.6V for VDDIOP (Peripheral I/Os) and for VDDIOM (Memory I/Os)
Available in a 208-pin Green PQFP or 256-ball RoHS-compliant BGA Package
•
•
•
•
1. Description
The AT91RM9200 is a complete system-on-chip built around the ARM920T ARM Thumb pro-
cessor. It incorporates a rich set of system and application peripherals and standard interfaces
in order to provide a single-chip solution for a wide range of compute-intensive applications that
require maximum functionality at minimum power consumption at lowest cost.
The AT91RM9200 incorporates a high-speed on-chip SRAM workspace, and a low-latency
External Bus Interface (EBI) for seamless connection to whatever configuration of off-chip mem-
ories and memory-mapped peripherals is required by the application. The EBI incorporates
controllers for synchronous DRAM (SDRAM), Burst Flash and Static memories and features
specific circuitry facilitating the interface for NAND Flash/SmartMedia and Compact Flash.
The Advanced Interrupt Controller (AIC) enhances the interrupt handling performance of the
ARM920T processor by providing multiple vectored, prioritized interrupt sources and reducing
the time taken to transfer to an interrupt handler.
The Peripheral DMA Controller (PDC) provides DMA channels for all the serial peripherals,
enabling them to transfer data to or from on- and off-chip memories without processor interven-
tion. This reduces the processor overhead when dealing with transfers of continuous data
streams.The AT91RM9200 benefits from a new generation of PDC which includes dual pointers
that simplify significantly buffer chaining.
The set of Parallel I/O (PIO) controllers multiplex the peripheral input/output lines with general-
purpose data I/Os for maximum flexibility in device configuration. An input change interrupt,
open drain capability and programmable pull-up resistor is included on each line.
The Power Management Controller (PMC) keeps system power consumption to a minimum by
selectively enabling/disabling the processor and various peripherals under software control. It
uses an enhanced clock generator to provide a selection of clock signals including a slow clock
(32 kHz) to optimize power consumption and performance at all times.
The AT91RM9200 integrates a wide range of standard interfaces including USB 2.0 Full Speed
Host and Device and Ethernet 10/100 Base-T Media Access Controller (MAC), which provides
connection to a extensive range of external peripheral devices and a widely used networking
layer. In addition, it provides an extensive set of peripherals that operate in accordance with sev-
eral industry standards, such as those used in audio, telecom, Flash Card, infrared and Smart
Card applications.
To complete the offer, the AT91RM9200 benefits from the integration of a wide range of debug
features including JTAG-ICE, a dedicated UART debug channel (DBGU) and an embedded real
time trace. This enables the development and debug of all applications, especially those with
real-time constraints.
2
AT91RM9200
1768I–ATARM–09-Jul-09
AT91RM9200
2. Block Diagram
Bold arrows (
Figure 2-1.
AT91RM9200 Block Diagram
NRST
JTAGSEL
TDI
TDO
TMS
TCK
NTRST
Reset
and
Test
ICE
JTAG
Scan
Instruction Cache
16K bytes
Data Cache
16K bytes
) indicate master-to-slave dependency.
TST0-TST1
ARM920T Core
ETM
MMU
TSYNC
PIO
TCLK
TPS0 - TPS2
TPK0 - TPK15
BMS
PIO
FIQ
IRQ0-IRQ6
PCK0-PCK3
PLLRCB
PLLRCA
XIN
XOUT
AIC
Fast SRAM
16K bytes
Address
Decoder
Abort
Status
EBI
CompactFlash
NAND Flash
SmartMedia
PLLB
PLLA
PMC
OSC
Peripheral
Bridge
System
Timer
Peripheral
DMA
Controller
Fast ROM
128K bytes
Misalignment
Detector
Bus
Arbiter
SDRAM
Controller
XIN32
XOUT32
DRXD
PIO
Memory
Controller
DBGU
PDC
DTXD
Static
Memory
Controller
PIOA/PIOB/PIOC/PIOD
Controller
DMA
FIFO
USB Host
FIFO
Transceiver
PIO
OSC
RTC
Burst
Flash
Controller
D0-D15
A0/NBS0
A1/NBS2/NWR2
A2-A15/A18-A22
A16/BA0
A17/BA1
NCS0/BFCS
NCS1/SDCS
NCS2
NCS3/SMCS
NRD/NOE/CFOE
NWR0/NWE/CFWE
NWR1/NBS1/CFIOR
NWR3/NBS3/CFIOW
SDCK
SDCKE
RAS-CAS
SDWE
SDA10
BFRDY/SMOE
BFCK
BFAVD
BFBAA/SMWE
BFOE
BFWE
A23-A24
A25/CFRNW
NWAIT
NCS4/CFCS
NCS5/CFCE1
NCS6/CFCE2
NCS7
D16-D31
HDMA
HDPA
HDMB
HDPB
DDM
DDP
Transceiver
USB Device
DMA
FIFO
ETXCK-ERXCK-EREFCK
ETXEN-ETXER
ECRS-ECOL
ERXER-ERXDV
ERX0-ERX3
ETX0-ETX3
EMDC
EMDIO
EF100
TF0
TK0
TD0
RD0
RK0
RF0
TF1
TK1
TD1
RD1
RK1
RF1
TF2
TK2
TD2
RD2
RK2
RF2
TCLK0
TCLK1
TCLK2
TIOA0
TIOB0
TIOA1
TIOB1
TIOA2
TIOB2
TCLK3
TCLK4
TCLK5
TIOA3
TIOB3
TIOA4
TIOB4
TIOA5
TIOB5
MCCK
MCCDA
MCDA0-MCDA3
MCCDB
MCDB0-MCDB3
RXD0
TXD0
SCK0
RTS0
CTS0
RXD1
TXD1
SCK1
RTS1
CTS1
DSR1
DTR1
DCD1
RI1
RXD2
TXD2
SCK2
RTS2
CTS2
RXD3
TXD3
SCK3
RTS3
CTS3
NPCS0
NPCS1
NPCS2
NPCS3
MISO
MOSI
SPCK
TWD
MCI
PDC
Ethernet MAC 10/100
APB
USART0
PDC
PDC
USART1
PIO
PIO
PIO
SSC0
SSC1
PDC
PDC
USART2
PDC
PDC
SSC2
USART3
PDC
Timer Counter
TC0
TC1
TC2
SPI
Timer Counter
PDC
TC3
TWI
TC4
TC5
TWCK
3
1768I–ATARM–09-Jul-09
3. Signal Description
Table 3-1.
Pin Name
Signal Description by Peripheral
Function
Power
Type
Active
Level
Comments
VDDIOM
VDDIOP
VDDPLL
VDDCORE
VDDOSC
GND
GNDPLL
GNDOSC
Memory I/O Lines Power Supply
Peripheral I/O Lines Power Supply
Oscillator and PLL Power Supply
Core Chip Power Supply
Oscillator Power Supply
Ground
PLL Ground
Oscillator Ground
Power
Power
Power
Power
Power
Ground
Ground
Ground
3.0V to 3.6V
3.0V to 3.6V
1.65V to 1.95V
1.65V to 1.95V
1.65V to 1.95V
Clocks, Oscillators and PLLs
XIN
XOUT
XIN32
XOUT32
PLLRCA
PLLRCB
PCK0 - PCK3
Main Crystal Input
Main Crystal Output
32KHz Crystal Input
32KHz Crystal Output
PLL A Filter
PLL B Filter
Programmable Clock Output
ICE and JTAG
TCK
TDI
TDO
TMS
NTRST
JTAGSEL
Test Clock
Test Data In
Test Data Out
Test Mode Select
Test Reset Signal
JTAG Selection
ETM
™
TSYNC
TCLK
TPS0 - TPS2
TPK0 - TPK15
Trace Synchronization Signal
Trace Clock
Trace ARM Pipeline Status
Trace Packet Port
Reset/Test
NRST
TST0 - TST1
Microcontroller Reset
Test Mode Select
Input
Input
Low
No on-chip pull-up, Schmitt trigger
Must be tied low for normal
operation, Schmitt trigger
Output
Output
Output
Output
Input
Input
Output
Input
Input
Input
Low
Schmitt trigger
Internal Pull-up, Schmitt trigger
Tri-state
Internal Pull-up, Schmitt trigger
Internal Pull-up, Schmitt trigger
Schmitt trigger
Input
Output
Input
Output
Input
Input
Output
4
AT91RM9200
1768I–ATARM–09-Jul-09
AT91RM9200
Table 3-1.
Pin Name
Signal Description by Peripheral
Function
Memory Controller
Type
Active
Level
Comments
BMS
Boot Mode Select
Debug Unit
Input
DRXD
DTXD
Debug Receive Data
Debug Transmit Data
AIC
Input
Output
Debug Receive Data
Debug Transmit Data
IRQ0 - IRQ6
FIQ
External Interrupt Inputs
Fast Interrupt Input
PIO
Input
Input
PA0 - PA31
PB0 - PB29
PC0 - PC31
PD0 - PD27
Parallel IO Controller A
Parallel IO Controller B
Parallel IO Controller C
Parallel IO Controller D
EBI
I/O
I/O
I/O
I/O
Pulled-up input at reset
Pulled-up input at reset
Pulled-up input at reset
Pulled-up input at reset
D0 - D31
A0 - A25
Data Bus
Address Bus
SMC
I/O
Output
Pulled-up input at reset
0 at reset
NCS0 - NCS7
NWR0 - NWR3
NOE
NRD
NUB
NLB
NWE
NWAIT
NBS0 - NBS3
Chip Select Lines
Write Signal
Output Enable
Read Signal
Upper Byte Select
Lower Byte Select
Write Enable
Wait Signal
Byte Mask Signal
Output
Output
Output
Output
Output
Output
Output
Input
Output
EBI for CompactFlash Support
Low
Low
Low
Low
Low
Low
Low
Low
Low
1 at reset
1 at reset
1 at reset
1 at reset
1 at reset
1 at reset
1 at reset
1 at reset
CFCE1 - CFCE2
CFOE
CFWE
CFIOR
CFIOW
CFRNW
CFCS
CompactFlash Chip Enable
CompactFlash Output Enable
CompactFlash Write Enable
CompactFlash IO Read
CompactFlash IO Write
CompactFlash Read Not Write
CompactFlash Chip Select
Output
Output
Output
Output
Output
Output
Output
Low
Low
Low
Low
Low
Low
5
1768I–ATARM–09-Jul-09
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