NCP3020A, NCP3020B,
NCV3020A, NCV3020B
Synchronous PWM Controller
The NCP3020 is a PWM device designed to operate from a wide
input range and is capable of producing an output voltage as low as
0.6 V. The NCP3020 provides integrated gate drivers and an internally
set 300 kHz (NCP3020A) or 600 kHz (NCP3020B) oscillator. The
NCP3020 also has an externally compensated transconductance error
amplifier with an internally fixed soft−start. Protection features
include lossless current limit and short circuit protection, output
overvoltage protection, output undervoltage protection, and input
undervoltage lockout. The NCP3020 is currently available in a
SOIC−8 package.
Features
http://onsemi.com
8
1
SOIC−8 NB
CASE 751
•
•
•
•
•
•
•
•
•
Input Voltage Range from 4.7 V to 28 V
300 kHz Operation (NCP3020B – 600 kHz)
0.6 V Internal Reference Voltage
Internally Programmed 6.8 ms Soft−Start (NCP3020B – 4.4 ms)
Current Limit and Short Circuit Protection
Transconductance Amplifier with External Compensation
Input Undervoltage Lockout
Output Overvoltage and Undervoltage Detection
NCV Prefix for Automotive and Other Applications Requiring Site
and Change Controls
•
This is a Pb−Free Device
V
IN
C
IN
C
BST
VCC
BST
HSDR
COMP
R
C
C
C2
C
C1
VSW
LSDR
GND
R
ISET
Q2
R
FB1
R
FB2
C
0
Q1
L
0
Vout
MARKING DIAGRAM
8
3020x
ALYW
G
1
3020x
A
L
Y
W
G
= Specific Device Code
x = A or B
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
PIN CONNECTIONS
V
CC
COMP
FB
GND
BST
HSDR
VSW
LSDR
ORDERING INFORMATION
Device
NCP3020ADR2G
NCP3020BDR2G
NCV3020ADR2G
Package
Shipping
†
SOIC−8 2500 / Tape & Reel
(Pb−Free)
SOIC−8 2500 / Tape & Reel
(Pb−Free)
SOIC−8 2500 / Tape & Reel
(Pb−Free)
SOIC−8 2500 / Tape & Reel
(Pb−Free)
FB
Figure 1. Typical Application Circuit
NCV3020BDR2G
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
©
Semiconductor Components Industries, LLC, 2013
January, 2013
−
Rev. 6
1
Publication Order Number:
NCP3020/D
NCP3020A, NCP3020B, NCV3020A, NCV3020B
VCC
INTERNAL BIAS
POR/STARTUP
VC
THERMAL SD
BOOST
CLAMP
BST
OSCILLATOR
CLK/
DMAX/
SOFT
START
RAMP
1.5 V
+
−
GATE
DRIVE
LOGIC
LEVEL
SHIFT
VCC
CURRENT
LIMIT
ISET
VC
SAMPLE &
HOLD
HSDR
VSW
COMP
REF
OTA
FB
+
−
+
−
PWM
COMP
LSDR
OOV
OUV
BST_CHRG
GND
Figure 2. NCP3020 Block Diagram
PIN FUNCTION DESCRIPTION
Pin
1
2
Pin Name
V
CC
COMP
Description
The V
CC
pin is the main voltage supply input. It is also used in conjunction with the VSW pin to sense current
in the high side MOSFET.
The COMP pin connects to the output of the Operational Transconductance Amplifier (OTA) and the positive
terminal of the PWM comparator. This pin is used in conjunction with the FB pin to compensate the voltage
mode control feedback loop.
The FB pin is connected to the inverting input of the OTA. This pin is used in conjunction with the COMP pin to
compensate the voltage mode control feedback loop.
Ground Pin
The LSDR pin is connected to the output of the low side driver which connects to the gate of the low side
N−FET. It is also used to set the threshold of the current limit circuit (I
SET
) by connecting a resistor from LSDR
to GND.
The VSW pin is the return path for the high side driver. It is also used in conjunction with the V
CC
pin to sense
current in the high side MOSFET.
The HSDR pin is connected to the output of the high side driver which connects to the gate of the high side
N−FET.
The BST pin is the supply rail for the gate drivers. A capacitor must be connected between this pin and the
VSW pin.
3
4
5
FB
GND
LSDR
6
7
8
VSW
HSDR
BST
http://onsemi.com
2
NCP3020A, NCP3020B, NCV3020A, NCV3020B
ABSOLUTE MAXIMUM RATINGS
(measured vs. GND pin 8, unless otherwise noted)
Rating
High Side Drive Boost Pin
Boost to V
SW
differential voltage
COMP
Feedback
High−Side Driver Output
Low−Side Driver Output
Main Supply Voltage Input
Switch Node Voltage
Maximum Average Current
V
CC
, BST, HSDRV, LSDRV, V
SW
, GND
Operating Junction Temperature Range (Note 1)
Maximum Junction Temperature
Storage Temperature Range
Thermal Characteristics (Note 2)
SOIC−8 Plastic Package
Thermal Resistance Junction−to−Air
Lead Temperature Soldering (10 sec): Reflow (SMD styles only) Pb−Free
(Note 3)
Symbol
BST
BST−V
SW
COMP
FB
HSDR
LSDR
V
CC
V
SW
I
max
T
J
T
J(MAX)
T
stg
V
MAX
45
13.2
5.5
5.5
40
13.2
40
40
130
−40
to +140
+150
−55
to +150
V
MIN
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−0.6
Unit
V
V
V
V
V
V
V
V
mA
°C
°C
°C
R
qJA
R
F
165
260 Peak
°C/W
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The maximum package power dissipation limit must not be exceeded.
P
D
+
T
J(max)
*
T
A
R
qJA
2. When mounted on minimum recommended FR−4 or G−10 board
3. 60−180 seconds minimum above 237°C.
http://onsemi.com
3
NCP3020A, NCP3020B, NCV3020A, NCV3020B
ELECTRICAL CHARACTERISTICS
(
−40°C
< T
J
< +125°C, V
CC
= 12 V, for min/max values unless otherwise noted)
Characteristic
Input Voltage Range
SUPPLY CURRENT
V
CC
Supply Current
V
CC
Supply Current
NCP3020A
NCP3020B
V
FB
= 0.55 V, Switching, V
CC
= 4.7 V
V
FB
= 0.55 V, Switching, V
CC
= 28 V
V
FB
= 0.55 V, Switching, V
CC
= 4.7 V
V
FB
= 0.55 V, Switching, V
CC
= 28 V
UNDER VOLTAGE LOCKOUT
UVLO Rising Threshold
UVLO Falling Threshold
OSCILLATOR
Oscillator Frequency
Oscillator Frequency
Ramp−Amplitude Voltage
Ramp Valley Voltage
PWM
Minimum Duty Cycle
Maximum Duty Cycle
Soft Start Ramp Time
NCP3020A
NCP3020B
NCP3020A
NCP3020B
V
FB
= V
COMP
(Note 4)
−
80
75
−
−
7.0
84
80
6.8
4.4
−
−
−
−
−
%
%
ms
NCP3020A
NCP3020B
T
J
= +25°C, 4.7 V
v
V
CC
v
28 V
T
J
=
−40°C
to +125°C, 4.7 V
v
V
CC
v
28 V
T
J
= +25°C, 4.7 V
v
V
CC
v
28 V
T
J
=
−40°C
to +125°C, 4.7 V
v
V
CC
v
28 V
V
peak
−
V
alley
(Note 4)
250
240
550
530
−
0.46
300
300
600
600
1.5
0.70
350
360
650
670
−
0.88
kHz
kHz
kHz
kHz
V
V
V
CC
Rising Edge
V
CC
Falling Edge
4.0
3.5
4.3
3.9
4.7
4.3
V
V
−
−
−
−
5.5
7.0
5.9
7.8
8.0
11
10
13
mA
mA
mA
mA
Conditions
−
Min
4.7
Typ
Max
28
Unit
V
ERROR AMPLIFIER (GM)
Transconductance
Open Loop dc Gain
Output Source Current
Output Sink Current
FB Input Bias Current
Feedback Voltage
COMP High Voltage
COMP Low Voltage
OUTPUT VOLTAGE FAULTS
Feedback OOV Threshold
Feedback OUV Threshold
OVERCURRENT
ISET Source Current
Current Limit Set Voltage (Note 5)
4.
5.
6.
7.
T
J
= 25°C, R
SET
= 22.5 kW
7.0
140
13
240
18
360
mA
mV
0.66
0.42
0.75
0.45
0.84
0.48
V
V
T
J
= 25°C
4.7 V < V
CC
< V
IN
< 28 V,
−40°C
< T
J
< +125°C
V
FB
= 0.55 V
V
FB
= 0.65 V
(Notes 4 and 6)
V
FB
= 545 mV
V
FB
= 655 mV
0.9
−
45
45
−
0.591
0.588
4.0
−
1.4
70
75
75
0.5
0.6
0.6
4.4
72
1.9
−
100
100
500
0.609
0.612
5.0
250
mS
dB
mA
mA
nA
V
V
V
mV
Guaranteed by design.
The voltage sensed across the high side MOSFET during conduction.
This assumes 100 pF capacitance to ground on the COMP Pin and a typical internal R
o
of > 10 MW.
This is not a protection feature.
http://onsemi.com
4
NCP3020A, NCP3020B, NCV3020A, NCV3020B
ELECTRICAL CHARACTERISTICS
(
−40°C
< T
J
< +125°C, V
CC
= 12 V, for min/max values unless otherwise noted)
Characteristic
GATE DRIVERS AND BOOST CLAMP
HSDRV Pullup Resistance
HSDRV Pulldown Resistance
LSDRV Pullup Resistance
LSDRV Pulldown Resistance
HSDRV Falling to LSDRV Rising
Delay
LSDRV Falling to HSDRV Rising
Delay
Boost Clamp Voltage
THERMAL SHUTDOWN
Thermal Shutdown
Hysteresis
4.
5.
6.
7.
(Notes 4 and 7)
(Notes 4 and 7)
−
−
165
20
−
−
°C
°C
T
J
= 25°C, V
CC
= 8 V, V
BST
= 7.5 V, V
SW
= GND
100 mA out of HSDR pin
T
J
= 25°C, V
CC
= 8 V, V
BST
= 7.5 V, V
SW
= GND
100 mA into HSDR pin
T
J
= 25°C, V
CC
= 8 V, V
BST
= 7.5 V, V
SW
= GND
100 mA out of LSDR pin
T
J
= 25°C, V
CC
= 8 V, V
BST
= 7.5 V, V
SW
= GND
100 mA into LSDR pin
V
IN
= 12 V, V
SW
= GND, V
COMP
= 1.3 V
V
IN
= 12 V, V
SW
= GND, V
COMP
= 1.3 V
V
IN
= 12 V, V
SW
= GND, V
COMP
= 1.3 V
5.0
2.0
5.0
1.0
50
60
5.5
11
5.0
9.0
3.0
80
80
7.5
20
11.5
16
6.0
110
120
9.6
W
W
W
W
ns
ns
V
Conditions
Min
Typ
Max
Unit
Guaranteed by design.
The voltage sensed across the high side MOSFET during conduction.
This assumes 100 pF capacitance to ground on the COMP Pin and a typical internal R
o
of > 10 MW.
This is not a protection feature.
http://onsemi.com
5
京公网安备 11010802033920号
EEWORLD
