EEWORLDEEWORLDEEWORLD

Part Number

Search

A1020B-PL44C

Description
FPGA, 547 CLBS, 2000 GATES, 45 MHz, PQCC44
CategoryProgrammable logic devices    Programmable logic   
File Size546KB,98 Pages
ManufacturerActel
Websitehttp://www.actel.com/
Download Datasheet Parametric View All

A1020B-PL44C Overview

FPGA, 547 CLBS, 2000 GATES, 45 MHz, PQCC44

A1020B-PL44C Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerActel
package instructionQCCJ, LDCC44,.7SQ
Reach Compliance Codecompli
Other featuresMAX 34 I/OS
maximum clock frequency45 MHz
Combined latency of CLB-Max4.5 ns
JESD-30 codeS-PQCC-J44
JESD-609 codee0
length16.51 mm
Humidity sensitivity level3
Configurable number of logic blocks547
Equivalent number of gates2000
Number of entries69
Number of logical units547
Output times69
Number of terminals44
Maximum operating temperature70 °C
Minimum operating temperature
organize547 CLBS, 2000 GATES
Package body materialPLASTIC/EPOXY
encapsulated codeQCCJ
Encapsulate equivalent codeLDCC44,.7SQ
Package shapeSQUARE
Package formCHIP CARRIER
Peak Reflow Temperature (Celsius)225
power supply5 V
Programmable logic typeFIELD PROGRAMMABLE GATE ARRAY
Certification statusNot Qualified
Maximum seat height4.445 mm
Maximum supply voltage5.25 V
Minimum supply voltage4.75 V
Nominal supply voltage5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationQUAD
Maximum time at peak reflow temperature30
width16.51 mm
v3.0
HiRel FPGAs
Fe a t ur es
• Low-Power 0.8µ CMOS Technology
32 0 0D X Fe a t ur es
• Highly Predictable Performance with 100% Automatic
Placement and Routing
• Device Sizes from 1,200 to 20,000 Gates
• Up to 6 Fast, Low-Skew Clock Networks
• Up to 202 User-Programmable I/O Pins
More Than 500 Macro Functions
Up to 1,276 Dedicated Flip-Flops
I/O Drive to 10 mA
Devices Available to DSCC SMD
CQFP and CPGA Packaging
Nonvolatile, User Programmable
Logic Fully Tested Prior to Shipment
100% Military Temperature Tested (–55°C to +125°C)
QML Certified Devices
• 100 MHz System Logic Integration
• Highest Speed FPGA SRAM, up to 2.5 kbits Configurable
Dual-Port SRAM
• Fast Wide-Decode Circuitry
• Low-Power 0.6µ CMOS Technology
12 0 0X L Fe at ure s
• Pin for Pin Compatible with ACT 2
• System Performance to 50 MHz over Military Temperature
• Low-Power 0.6µ CMOS Technology
A CT 2 Fe at ure s
• Proven Reliability Data Available
• Successful Military/Avionics Supplier for Over 10 Years
A CT 3 Fe at ure s
• Best-Value, High-Capacity FPGA Family
• System Performance to 40 MHz over Military Temperature
• Low-Power 1.0µ CMOS Technology
A CT 1 Fe at ure s
• Highest-Performance, Highest-Capacity FPGA Family
• System Performance to 60 MHz over Military Temperature
• Lowest-Cost FPGA Family
• System Performance to 20 MHz over Military Temperature
• Low-Power 1.0µ CMOS Technology
Pr od uc t F am i l y P r o f i l e
(more devices on
page 2)
Family
Device
Capacity
System Gates
Logic Gates
SRAM Bits
Logic Modules
S-Modules
C-Modules
Decode
Flip-Flops (Maximum)
User I/Os (Maximum)
Performance
System Speed (maximum)
Packages (by Pin Count)
CPGA
CQFP
3200DX
A32100DX
15,000
10,000
2,048
1,362
700
662
20
738
152
55 MHz
A32200DX
30,000
20,000
2,560
2,414
1,230
1,184
24
1,276
202
55 MHz
A1425A
3,750
2,500
NA
310
160
150
NA
435
100
60 MHz
133
132
ACT 3
A1460A
9,000
6,000
NA
848
432
416
NA
976
168
60 MHz
207
196
A14100A
15,000
10,000
NA
1,377
697
680
NA
1,493
228
60 MHz
257
256
1200XL
A1280XL
12,000
8,000
1,232
624
608
NA
998
140
50 MHz
176
172
84
208, 256
J an u a r y 2 0 0 0
1
© 2000 Actel Corporation
[Nucleo experience] STM32L053 Nucleo mbed offline compilation (keil)
It's been nearly a month since I got the stm32L053R8 nucleo development board. I used the ST library to test the performance of the board and I feel that the board is pretty good (I bought it in a gro...
晓枫VS枯叶 stm32/stm8
11 tips for participating in e-sports competitions in 2009 [Repost]
[i=s]This post was last edited by paulhyde on 2014-9-15 09:13[/i]Many of my classmates often ask me about how to participate in e-contests and how to prepare. They plan to participate in the national ...
lk972105 Electronics Design Contest
(Urgent help) Summary of synchronization and network connection problems encountered when testing PDA in CE5.0 environment (waiting for answers online). . .
Hello everyone, I have a few questions to ask you. I just started programming in the CE5.0 environment and encountered several problems with the environment configuration: The environment is C#.Net200...
lanqier396 Embedded System
MSP430 microcontroller PWM source code routine
PWM source code example, good example....
伤逝 Microcontroller MCU
The data has been burned into FLASH, so why can't it run offline?
Why is there no one helping me?...
lc258 Microcontroller MCU
Serial communication between CPLD and AD chip
I am a newbie, and I want to ask you all the seniors, now I need to use ALTERA's MAXV CPLD to drive the ADS8325 chip, serial communication, the data is 16 bits, do I need to use Verilog to write a com...
duanxianzhuang FPGA/CPLD

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 667  2632  1630  1718  1497  14  53  33  35  31 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号