X9420WS16IZ-T1 datasheet, PDF - EEWORLD Datasheet

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X9420WS16IZ-T1: Description10K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDSO16, 0.300 INCH, ROHS COMPLIANT, PLASTIC, MS-013AA, SOIC-16; CategoryAnalog mixed-signal IC converter; File Size309KB，19 Pages; ManufacturerIntersil ( Renesas ); Websitehttp://www.intersil.com/cda/home/; Environmental Compliance

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X9420WS16IZ-T1 Overview

10K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDSO16, 0.300 INCH, ROHS COMPLIANT, PLASTIC, MS-013AA, SOIC-16

X9420WS16IZ-T1 Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Objectid	2104575844
Parts packaging code	SOIC
package instruction	SOP, SOP16,.4
Contacts	16
Reach Compliance Code	compliant
ECCN code	EAR99
Other features	NONVOLATILE MEMORY
control interface	3-WIRE SERIAL
Converter type	DIGITAL POTENTIOMETER
JESD-30 code	R-PDSO-G16
JESD-609 code	e3
length	10.3 mm
Humidity sensitivity level	5
Number of functions	1
Number of positions	64
Number of terminals	16
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP16,.4
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	260
power supply	5 V
Certification status	Not Qualified
resistance law	LINEAR
Maximum resistor tolerance	20%
Maximum resistor terminal voltage	5.5 V
Minimum resistor terminal voltage	-5.5 V
Maximum seat height	2.65 mm
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Nominal temperature coefficient	300 ppm/°C
Temperature level	INDUSTRIAL
Terminal surface	Matte Tin (Sn) - annealed
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
Nominal total resistance	10000 Ω
width	7.5 mm

X9420WS16IZ-T1 Preview

I GNS

D ES

OR N RODUC 11

D ED

MEN STITUT 11, ISL9

COM

Data Sheet

T RE IBLE SU 19, ISL9

POS 6, ISL22

241

ISL2

X9420

Low Noise/Low Power/SPI Bus

April 26, 2006

FN8195.1

Single Digitally Controlled (XDCP™)

Potentiometer

FEATURES

• Solid-State Potentiometer

• SPI Serial Interface

• Register Oriented Format

—Direct read/write/transfer wiper positions

—Store as many as four positions per

potentiometer

• Power Supplies

—V

= 2.7V to 5.5V

—V+ = 2.7V to 5.5V

—V– = -2.7V to -5.5V

• Low Power CMOS

—Standby current < 1µA

• High Reliability

—Endurance–100,000 data changes per bit per

—Register data retention–100 years

• 8-bytes of Nonvolatile EEPROM Memory

• 10kΩ or 2.5kΩ Resistor Arrays

• Resolution: 64 Taps Each Pot

• 14 Ld TSSOP and 16 Ld SOIC Packages

• Pb-Free Plus Anneal Available (RoHS Compliant)

BLOCK DIAGRAM

HOLD

SCK

DESCRIPTION

The X9420 integrates a single digitally controlled

potentiometers (XDCP) on a monolithic CMOS

integrated microcircuit.

The digitally controlled potentiometer is implemented

using 63 resistive elements in a series array. Between

each element are tap points connected to the wiper

terminal through switches. The position of the wiper on

the array is controlled by the user through the SPI bus

interface. The potentiometer has associated with it a

volatile Wiper Counter Register (WCR) and 4

nonvolatile Data Registers (DR0:DR3) that can be

directly written to and read by the user. The contents

of the WCR controls the position of the wiper on the

resistor array through the switches. Power-up recalls

the contents of DR0 to the WCR.

The XDCP can be used as a three-terminal

potentiometer or as a two-terminal variable resistor in

a wide variety of applications including control,

parameter adjustments, and signal processing.

Interface

and

Control

Circuitry

R0 R1

Data

R2 R3

Wiper

Counter

(WCR)

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

X9420

Ordering Information

PART NUMBER

X9420WS16*

X9420WS16Z* (Note)

X9420WS16I*

X9420WS16IZ* (Note)

X9420WV14*

X9420WV14Z* (Note)

X9420WV14I*

X9420WV14IZ* (Note)

X9420YS16*

X9420YS16Z* (Note)

X9420YS16I*

X9420YS16IZ* (Note)

X9420YV14*

X9420YV14Z* (Note)

X9420YV14I*

X9420YV14IZ* (Note)

X9420WS16-2.7*

PART

MARKING

X9420WS

X9420WS Z

X9420WS I

X9420WS ZI

X9420 W

X9420 WZ

X9420 WI

X9420 WZI

X9420YS

X9420YS Z

X9420YS I

X9420YS ZI

X9420 Y

X9420 YZ

X9420 YI

X9420 YZI

X9420WS F

2.7 to 5.5

2.5

POTENTIOMETER

ORGANIZATION TEMP. RANGE

(k)

(°C)

LIMITS (V)

5 ±10%

0 to +70

-40 to +85

0 to +70

-40 to +85

0 to +70

-40 to +85

0 to +70

-40 to +85

0 to +70

-40 to +85

0 to +70

-40 to +85

2.7 to 5.5

2.5

0 to +70

-40 to +85

0 to +70

-40 to +85

PACKAGE

16 Ld SOIC (300 mil)

16 Ld SOIC (300 mil) (Pb-free)

16 Ld SOIC (300 mil)

16 Ld SOIC (300 mil) (Pb-free)

14 Ld TSSOP (4.4mm)

PKG.

DWG. #

M16.3

M14.173

14 Ld TSSOP (4.4mm) (Pb-free) M14.173

14 Ld TSSOP (4.4mm)

M14.173

14 Ld TSSOP (4.4mm) (Pb-free) M14.173

16 Ld SOIC (300 mil)

16 Ld SOIC (300 mil) (Pb-free)

16 Ld SOIC (300 mil)

16 Ld SOIC (300 mil) (Pb-free)

14 Ld TSSOP (4.4mm)

M16.3

M14.173

14 Ld TSSOP (4.4mm) (Pb-free) M14.173

14 Ld TSSOP (4.4mm)

M14.173

14 Ld TSSOP (4.4mm) (Pb-free) M14.173

16 Ld SOIC (300 mil)

16 Ld SOIC (300 mil) (Pb-free)

16 Ld SOIC (300 mil)

16 Ld SOIC (300 mil) (Pb-free)

14 Ld TSSOP (4.4mm)

M16.3

M14.173

X9420WS16Z-2.7* (Note) X9420WS ZF

X9420WS16I-2.7*

X9420WS16IZ-2.7*

(Note)

X9420WV14-2.7*

X9420WS G

X9420WS ZG

X9420 WF

X9420WV14Z-2.7* (Note) X9420 WZF

X9420WV14I-2.7*

X9420WV14IZ-2.7*

(Note)

X9420YS16-2.7*

X9420 WG

X9420 WZG

X9420YS F

14 Ld TSSOP (4.4mm) (Pb-free) M14.173

14 Ld TSSOP (4.4mm)

M14.173

14 Ld TSSOP (4.4mm) (Pb-free) M14.173

16 Ld SOIC (300 mil)

16 Ld SOIC (300 mil) (Pb-free)

16 Ld SOIC (300 mil)

16 Ld SOIC (300 mil) (Pb-free)

14 Ld TSSOP (4.4mm)

M16.3

M14.173

X9420YS16Z-2.7* (Note) X9420YS ZF

X9420YS16I-2.7*

X9420YS G

X9420YS16IZ-2.7* (Note) X9420YS ZG

X9420YV14-2.7*

X9420 YF

X9420YV14Z-2.7* (Note) X9420 YZF

X9420YV14I-2.7*

X9420 YG

14 Ld TSSOP (4.4mm) (Pb-free) M14.173

14 Ld TSSOP (4.4mm)

M14.173

X9420YV14IZ-2.7* (Note) X9420 YZG

*Add "T1" suffix for tape and reel.

14 Ld TSSOP (4.4mm) (Pb-free) M14.173

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate

termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL

classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

FN8195.1

April 26, 2006

X9420

PIN DESCRIPTIONS

Host Interface Pins

Serial Output (SO)

SO is a push/pull serial data output pin. During a read

cycle, data is shifted out on this pin. Data is clocked

out by the falling edge of the serial clock.

Serial Input

SI is the serial data input pin. All opcodes, byte

addresses and data to be written to the potentiometer

and pot register are input on this pin. Data is latched

by the rising edge of the serial clock.

Serial Clock (SCK)

The SCK input is used to clock data into and out of the

X9420.

Chip Select (CS)

When CS is HIGH, the X9420 is deselected and the

SO pin is at high impedance, and (unless an internal

write cycle is underway) the device will be in the

standby state. CS LOW enables the X9420, placing it

in the active power mode. It should be noted that after

a power-up, a HIGH to LOW transition on CS is

required prior to the start of any operation.

Hold (HOLD)

HOLD is used in conjunction with the CS pin to select

the device. Once the part is selected and a serial

sequence is underway, HOLD may be used to pause

the serial communication with the controller without

resetting the serial sequence. To pause, HOLD must

be brought LOW while SCK is LOW. To resume

communication, HOLD is brought HIGH, again while

SCK is LOW. If the pause feature is not used, HOLD

should be held HIGH at all times.

Device Address (A

)

The address inputs is used to set the least significant

bit of the 8-bit slave address. A match in the slave

address serial data stream must be made with the

address input in order to initiate communication with

the X9420. A maximum of 2 devices may occupy the

SPI serial bus.

Potentiometer Pins

, V

The V

and V

input are equivalent to the

terminal connections on either end of a mechanical

potentiometer.

The wiper output is equivalent to the wiper output of a

mechanical potentiometer.

Hardware Write Protect Input (WP)

The WP pin when LOW prevents nonvolatile writes to

the Data Registers. Writing to the Wiper Counter

Analog Supplies (V+, V-)

The analog supplies V+, V- are the supply voltages for

the XDCP analog section.

System/Digital Supply (V

)

is the supply voltage for the system/digital

section. V

is the system ground.

PIN CONFIGURATION

DIP/SOIC

X9420

V+

HOLD

SCK

V-

TSSOP

X9420

V+

HOLD

SCK

V-

FN8195.1

April 26, 2006

X9420

PIN NAMES

Symbol

SCK

SI, SO

HOLD

V+,V-

Serial Clock

Serial Data

Device Address

Potentiometer Pins (terminal equivalent)

Potentiometer Pins (wiper equivalent)

Hardware Write Protection

Serial Communication Pause

Analog Supplies

System Supply Voltage

System Ground

No Connection

Wiper Counter Register (WCR)

Description

The X9420 contains a Wiper Counter Register. The

WCR can be envisioned as a 6-bit parallel and serial

load counter with its outputs decoded to select one of

sixty-four switches along its resistor array. The

contents of the WCR can be altered in four ways: it

may be written directly by the host via the Write Wiper

Counter Register instruction (serial load); it may be

written indirectly by transferring the contents of one of

four associated data registers via the XFR Data

one step at a time by the Increment/ Decrement

instruction. Finally, it is loaded with the contents of its

data register zero (DR0) upon power-up.

The Wiper Counter Register is a volatile register; that

is, its contents are lost when the X9420 is powered-

down. Although the register is automatically loaded

with the value in DR0 upon power-up, this may be

different from the value present at power-down.

Data Registers

The potentiometer has four 6-bit nonvolatile Data

Registers. These can be read or written directly by the

host. Data can also be transferred between any of the

four Data Registers and the WCR. It should be noted all

operations changing data in one of the Data Registers is

a nonvolatile operation and will take a maximum of 10ms.

If the application does not require storage of multiple

settings for the potentiometer, the Data Registers can

be used as regular memory locations for system

parameters or user preference data.

Table 1. Data Registers, (6-bit), Nonvolatile

(MSB)

PRINCIPLES OF OPERATION

The X9420 is a highly integrated microcircuit

incorporating a resistor array and associated registers

and counter and the serial interface logic providing

direct communication between the host and the XDCP

potentiometer.

Serial Interface

The X9420 supports the SPI interface hardware

conventions. The device is accessed via the SI input

with data clocked in on the rising SCK. CS must be

LOW and the HOLD and WP pins must be HIGH

during the entire operation.

The SO and SI pins can be connected together, since

they have three state outputs. This can help to reduce

system pin count.

Array Description

The X9420 is comprised of one resistor array

containing 63 discrete resistive segments that are

connected in series. The physical ends of each array

are equivalent to the fixed terminals of a mechanical

potentiometer (V

and V

inputs).

At both ends of the array and between each resistor

segment is a CMOS switch connected to the wiper

) output. Within the individual array only one

switch may be turned on at a time.

These switches are controlled by a Wiper Counter

select, and enable, one of sixty-four switches. The block

diagram of the potentiometer is shown in Figure 1.

(LSB)

There are four 6-bit Data Registers associated with the

potentiometer.

– {D5~D0}: These bits are for general purpose Non-

volatile data storage or for storage of up to four dif-

ferent wiper values.

Table 2. Wiper Counter Register, (6-bit), Volatile

(MSB)

WP5 WP4 WP3 WP2 WP1 WP0

(LSB)

– {WP5~WP0}: These bits specify the wiper position

of the potentiometer.

FN8195.1

April 26, 2006

X9420

Figure 1. Detailed Potentiometer Block Diagram

Serial Data Path

From Interface

Circuitry

Serial

Bus

Input

Parallel

Bus

Input

Wiper

Counter

(WCR)

IF WCR = 00[H] THEN V

= V

IF WCR = 3F[H] THEN V

= V

UP/DN

Modified SCK

INC/DEC

Logic

UP/DN

CLK

Write in Process

The contents of the Data Registers are saved to

nonvolatile memory when the CS pin goes from LOW to

HIGH after a complete write sequence is received by

the device. The progress of this internal write operation

can be monitored by a Write In Process bit (WIP). The

WIP bit is read with a Read Status command.

INSTRUCTIONS

Address/Identification (ID) Byte

The first byte sent to the X9420 from the host,

following a CS going HIGH to LOW, is called the

Address or Identification byte. The most significant

four bits of the slave address are a device type

identifier, for the X9420 this is fixed as 0101[B] (refer

to Figure 2).

The least significant bit in the ID byte selects one of

two devices on the bus. The physical device address

is defined by the state of the A

input pin. The X9420

compares the serial data stream with the address

input state; a successful compare of the address bit is

required for the X9420 to successfully continue the

command sequence. The A

input can be actively

driven by a CMOS input signal or tied to V

or V

The remaining three bits in the ID byte must be set to 110.

Figure 2. Address/Identification Byte Format

Device Type

Identifier

Device Address

Instruction Byte

The next byte sent to the X9420 contains the

instruction and register pointer information. The four

most significant bits are the instruction. The next two

bits point to one of four data registers. The format is

shown below in Figure 3.

Figure 3. Instruction Byte Format

Select

Instructions

FN8195.1

April 26, 2006

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