Digital DC/DC Controller with Drivers and Auto
Compensation
ZL6105
The ZL6105 is a digital power controller with integrated
MOSFET drivers. Auto compensation eliminates the need for
manual compensation design work. Adaptive performance
optimization algorithms improve power conversion efficiency.
Zilker Labs Digital-DC™ technology enables a blend of power
conversion performance and power management features.
The ZL6105 is designed to be a flexible building block for DC
power and can be easily adapted to designs ranging from a
single-phase power supply operating from a 3.3V to a
multiphase current sharing supply operating from a 12V input.
The ZL6105 eliminates the need for complicated power supply
managers as well as numerous external discrete components.
The ZL6105 uses the I
2
C/SMBus™ with PMBus™ protocol for
communication with a host controller and the Digital-DC bus
for communication between Zilker Labs devices.
The ZL6105 is pin for pin compatible with the ZL2008. The
POLA V
OUT
table and compensation table have been removed.
A new single resistor V
OUT
table and the Auto Compensation
feature have been added.
Features
Power Conversion
• Efficient Synchronous Buck Controller
• Auto Compensating PID Filter
• Adaptive Light Load Efficiency Optimization
• 3V to 14V Input Range
• 0.54V to 5.5V Output Range (with margin)
• ±1% Output Voltage Accuracy
• Internal 3A MOSFET Drivers
• Fast Load Transient Response
• Current Sharing and Phase Interleaving
•
Snapshot™
Parameter Capture
• Pb-Free (RoHs Compliant)
Power Management
• Digital Soft-start/stop
• Power-Good/Enable
• Voltage Tracking, Sequencing and Margining
• Voltage, Current and Temperature Monitoring
• I
2
C/SMBus Interface, PMBus Compatible
• Output Voltage and Current Protection
• Internal Non-volatile Memory (NVM)
Related Literature*
(see page 34)
• See
AN2032,
“NLR Configuration for DDC Products”
• See
AN2033,
“Zilker Labs PMBus Command Set - DDC Products”
• See
AN2034,
“Configuring Current Sharing on the ZL2004
and ZL2006”
• See
AN2035,
“Compensation Using CompZL™”
Applications
• Servers/Storage Equipment
• Telecom/Datacom Equipment
• Power Supply Modules
EN PG PH_EN FC ILIM CFG UVLO V25
VR VDD
100
95
V
OUT
= 3.3V
V
OUT
= 1.5V
POWER
MANAGEMENT
DRIVER
NON-
VOLATILE
MEMORY
PWM
CONTROLLER
DDC
BST
GH
SW
GL
VSEN+
VSEN-
ISENA
ISENB
Efficiency (%)
V
SS
VTRK
MGN
SYNC
90
LDO
85
80
75
70
65
60
55
50
0
V
IN
= 12V
f
SW
= 400kHz
Circuit of Figure
3
4
2
4
6
8
10
12
14
16
18
20
CURRENT
SENSE
TEMP
SENSOR
SCL
SDA
SALRT
I
2
C
MONITOR
ADC
SA
XTEMP
PGND SGND DGND
Load Current (A)
FIGURE 1. BLOCK DIAGRAM
February 8, 2011
FN6906.3
FIGURE 2. EFFICIENCY vs LOAD CURRENT
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Copyright Intersil Americas Inc. 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1
ZL6105
Typical Application Circuit
The following application circuit represents a typical implementation of the ZL6105. For enable using the PMBus, it is recommended to
tie the enable pin (EN) to SGND.
F.B.
1
V
IN
12V
C
IN
3 x 10 µF
25 V
ENABLE
PHASE ENABLE
POWER GOOD OUTPUT
DDC Bus
3
C
V25
10 µF
4V
QH
PG
36
CFG2
35
PH_EN
34
EN
33
CFG1
32
MGN
31
DDC
30
XTEMP
29
V25
28
4.7 µF
25 V
DB
BAT54
VDD
27
BST
26
GH
25
SW
24
1 µF
16 V
CB
L
OUT
2.2 µH
C
OUT
2 x 47 µF
6.3 V
QL
C
VR
V
OUT
V25
1
DGND
2
SYNC
3
SA0
4
SA1
5
ILIM
ZL6105
PGND
23
GL
22
VR
21
ISENA
20
I
2
C/SMBus
2
6
CFG0
7
SCL
8
SDA
17
VSEN+
18
VSEN-
14
UVLO
16
VRTK
9
SALRT
10
FC0
11
FC1
12
V0
13
V1
470 µF
2.5 V
POS-CAP
ISENB
19
2*220 µF
6.3 V
100 m
RTN
15
SS
EPAD
SGND
4.7 µF
6.3 V
Ground unification
Notes:
1. Ferrite bead is optional for input noise suppression
2. The I
2
C/SMBus requires pull-up resistors. Please refer to the I
2
C/SMBus specifications for more details.
3. The DDC bus requires a pull-up resistor. The resistance will vary based on the capacitive loading of the bus (and on the number of devices
connected). The 10 k
Ω
default value, assuming a maximum of 100 pF per device, provides the necessary 1 µs pull-up rise time. Please refer to the
DDC Bus section for more details.
FIGURE 3. 12V TO 1.8V/16A APPLICATION CIRCUIT
2
FN6906.3
February 8, 2011
ZL6105
>
PG
EN
MGN
Input Voltage Bus
CFG(0,1,2)
SS
ILIM
V(0,1)
FC(0,1)
VDD
VR
VTRK
Power Management
NVM
MOSFET
Drivers
D-PWM
NLR
BST
SYNC
GEN
Digital
Compensator
SW
V
OUT
SYNC
PLL
ADC
ADC
Σ
+
-
VSEN
ISENB
ISENA
REFCN
DDC
SALRT
SDA
SCL
SA(0,1)
DAC
VDD
MUX
I
2
C
ADC
Communication
Voltage
Sensor
TEMP
Sensor
VSEN+
VSEN-
XTEMP
FIGURE 4. ZL6105 BLOCK DIAGRAM
3
FN6906.3
February 8, 2011
ZL6105
Pin Configuration
ZL6105
(36 LD QFN)
TOP VIEW
32 CFG1
31 MGN
30 DDC
29 XTEMP
34 PH_EN
35 CFG2
28 V25
27 VDD
26 BST
25 GH
24 SW
EXPOSED PADDLE*
23 PGND
22 GL
21 VR
20 ISENA
19 ISENB
FC0 10
FC1 11
V1 13
V0 12
UVLO 14
VSEN+ 17
VTRK 16
SS 15
VSEN- 18
36 PG
DGND 1
SYNC 2
SA0 3
SA1 4
ILIM 5
CFG0 6
SCL 7
SDA 8
SALRT 9
*CONNECT TO SGND
Pin Descriptions
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
LABEL
DGND
SYNC
SA0
SA1
ILIM
CFG0
SCL
SDA
SALRT
FC0
FC1
V0
V1
UVLO
SS
VTRK
VSEN+
VSEN-
ISENB
I, M
I, M
I
I
I
I
Undervoltage lockout selection. Sets the minimum value for V
DD
voltage to enable V
OUT
.
Soft start pin. Sets the output voltage ramp time during turn-on and turn-off. Sets the delay from when EN
is asserted until the output voltage starts to ramp.
Tracking sense input. Used to track an external voltage source.
Output voltage feedback. Connect to output regulation point.
Output voltage feedback. Connect to load return or ground regulation point.
Differential voltage input for current limit.
I
Output voltage selection pins. Used to set V
OUT
set-point and V
OUT
max.
I, M
I, M
I/O
I/O
O
I
TYPE
(Note 1)
PWR
I/O,M (Note 2)
I, M
DESCRIPTION
Digital ground. Common return for digital signals. Connect to low impedance ground plane.
Clock synchronization input. Used to set switching frequency of internal clock or for synchronization to
external frequency reference.
Serial address select pins. Used to assign unique SMBus address to each IC or to enable certain
management features.
Current limit select. Sets the overcurrent threshold voltage for ISENA and ISENB.
Configuration pin. Used to setup current sharing and non-linear response.
Serial clock. Connect to external host and/or to other ZL devices.
Serial data. Connect to external host and/or to other ZL devices.
Serial alert. Connect to external host if desired.
Loop compensation configuration pins.
4
33 EN
FN6906.3
February 8, 2011
ZL6105
Pin Descriptions
(Continued)
PIN
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
ePad
NOTES:
1. I = Input, O = Output, PWR = Power or Ground. M = Multi-mode pin dependents. (Refer to “Multi-mode Pins” on page 11).
2. The SYNC pin can be used as a logic pin, a clock input or a clock output.
3. V
DD
is measured internally and the value is used to modify the PWM loop gain.
LABEL
ISENA
VR
GL
PGND
SW
GH
BST
VDD (Note 3)
V25
XTEMP
DDC
MGN
CFG1
EN
PH_EN
CFG2
PG
SGND
TYPE
(Note 1)
I
PWR
O
PWR
PWR
O
PWR
PWR
PWR
I
I/O
I
I, M
I
I
I, M
O
PWR
DESCRIPTION
Differential voltage input for current limit. High voltage tolerant.
Internal 5V reference used to power internal drivers.
Low side FET gate drive.
Power ground. Connect to low impedance ground plane.
Drive train switch node.
High-side FET gate drive.
High-side drive boost voltage.
Supply voltage.
Internal 2.5V reference used to power internal circuitry.
External temperature sensor input. Connect to external 2N3904 diode connected transistor.
Digital-DC Bus. (Open Drain) Interoperability between Zilker Labs devices.
Signal that enables margining of output voltage.
Configuration pin. Used to setup clock synchronization and sequencing.
Enable input (active high). Pull-up to enable PWM switching and pull-down to disable PWM switching.
Phase enable input (active high). Pull-up to enable phase and pull-down to disable phase for current
sharing.
Configuration pin. Sets the phase offset (single-phase) or current sharing group position (multi-phase).
Power-good output.
Exposed thermal pad. Common return for analog signals; internal connection to SGND. Connect to low
impedance ground plane.
Ordering Information
PART NUMBER
(Notes 5, 6)
ZL6105ALAF
ZL6105ALAFT (Note 4)
ZL6105ALAFTK(Note 4)
ZL6105ALAF-01
ZL6105ALAFT-01 (Note 4)
ZL6105ALAFTK-01 (Note 4)
NOTES:
4. Please refer to
TB347
for details on reel specifications.
5. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-
free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
6. For Moisture Sensitivity Level (MSL), please see device information page for
ZL6105.
For more information on MSL please see techbrief
TB363.
6105
6105
6105
6105-01
6105-01
6105-01
PART
MARKING
TEMP. RANGE
(°C)
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
PACKAGE
(Pb-free)
36 Ld QFN
36 Ld QFN
36 Ld QFN
36 Ld QFN
36 Ld QFN
36 Ld QFN
PKG.
DWG. #
L36.6x6A
L36.6x6A
L36.6x6A
L36.6x6A
L36.6x6A
L36.6x6A
5
FN6906.3
February 8, 2011
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