24LC01B/02B
1K/2K 2.5V CMOS Serial EEPROMs
FEATURES
• Single supply with operation down to 2.5V
• Low power CMOS technology
- 1 mA active current typical
- 10
µ
A standby current typical at 5.5V
- 5
µ
A standby current typical at 3.0V
• Organized as a single block of 128 bytes (128 x 8)
or 256 bytes (256 x 8)
• Two wire serial interface bus, I
2
C
™
compatible
• 100kHz (2.5V) and 400kHz (5V) compatibility
• Self-timed write cycle (including auto-erase)
• Page-write buffer for up to 8 bytes
• 2 ms typical write cycle time for page-write
• Hardware write protect for entire memory
• Can be operated as a serial ROM
• Factory programming (QTP) available
• ESD protection > 3,000V
• 10,000,000 ERASE/WRITE cycles guaranteed
on 24LC01B
• 1,000,000 E/W cycles guaranteed on 24LC02B*
• Data retention > 200 years
• 8 pin DIP or SOIC package
• Available for extended temperature ranges
- Commercial
0˚C to +70˚C
- Industrial:
-40˚C to +85˚C
PACKAGE TYPE
DIP
A0
A1
A2
V
SS
1
2
3
4
8
7
6
5
V
CC
WP
SCL
SDA
24LC01B/02B
SOIC
A0
A1
A2
V
SS
1
2
3
4
8
7
6
5
V
CC
WP
SCL
SDA
24LC01B/02B
BLOCK DIAGRAM
WP
DESCRIPTION
The Microchip Technology Inc. 24LC01B and 24LC02B
are 1K bit and 2K bit Electrically Erasable PROMs. The
devices are organized as a single block of 128 x 8 bit
or 256 x 8 bit memory with a two wire serial interface.
Low voltage design permits operation down to 2.5 volts
with a standby and active currents of only 5
µ
A and 1
mA respectively. The 24LC01B and 24LC02B also
have page-write capability for up to 8 bytes of data.
The 24LC01B and 24LC02B are available in the stan-
dard 8-pin DIP and an 8-pin surface mount SOIC pack-
age.
HV GENERATOR
I/O
CONTROL
LOGIC
MEMORY
CONTROL
LOGIC
XDEC
EEPROM
ARRAY
PAGE LATCHES
SDA
SCL
YDEC
V
CC
V
SS
SENSE AMP
R/W CONTROL
*Future: 10,000,000 E/W cycles guaranteed.
I
2
C is a trademark of Phillips Corporation
©
1995 Microchip Technology Inc.
DS20071G-page 1
24LC01B/02B
1.0
ELECTRICAL CHARACTERISTICS
TABLE 1-1:
Name
V
SS
SDA
SCL
WP
V
CC
A0, A1, A2
PIN FUNCTION TABLE
Function
Ground
Serial Address/Data I/O
Serial Clock
Write Protect Input
+2.5V to 5.5V Power Supply
No Internal Connection
Maximum Ratings*
V
CC
........................................................................ 7.0V
All inputs and outputs w.r.t. V
SS
.....-0.6V to V
CC
+1.0V
Storage temperature ...........................-65˚C to +150˚C
Ambient temp. with power applied ......-65˚C to +125˚C
Soldering temperature of leads (10 seconds) ...+300˚C
ESD protection on all pins
......................................≥
4 kV
*Notice:
Stresses above those listed under “Maximum ratings”
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
TABLE 1-2:
DC CHARACTERISTICS
V
CC
= +2.5V to +5.5V
Parameter
Symbol
V
IH
V
IL
V
HYS
V
OL
I
LI
I
LO
C
IN
,
C
OUT
I
CC
Write
I
CC
Read
-10
-10
—
—
—
—
.05 V
CC
Min.
.7 V
CC
.3 V
CC
—
.40
10
10
10
3
1
30
100
Commercial (C): Tamb = 0˚C to +70˚C
Industrial
(I): Tamb = -40˚C to +85˚C
Max.
Units
V
V
V
V
µ
A
µ
A
pF
mA
mA
µ
A
µ
A
V
CC
= 3.0V, SDA = SCL = V
CC
V
CC
= 5.5V, SDA = SCL = V
CC
Note 1
I
OL
= 3.0 mA, V
CC
= 2.5V
V
IN
= .1V to 5.5V
V
OUT
= .1V to 5.5V
V
CC
= 5.0V (Note 1)
Tamb = 25˚C, F
CLK
= 1 MHz
V
CC
= 5.5V, SCL = 400 kHz
Conditions
WP, SCL and SDA pins:
High level input voltage
Low level input voltage
Hysteresis of Schmidt trigger inputs
Low level output voltage
Input leakage current
Output leakage current
Pin capacitance (all inputs/outputs)
Operating current
Standby current
I
CCS
Note 1:
This parameter is periodically sampled and not 100% tested.
FIGURE 1-1:
BUS TIMING START/STOP
V
HYS
SCL
T
SU:STA
SDA
T
HD:STA
T
SU:STO
START
STOP
DS20071G-page 2
©
1995 Microchip Technology Inc.
24LC01B/02B
TABLE 1-3:
AC CHARACTERISTICS
STANDARD
MODE
Min.
Clock frequency
Clock high time
Clock low time
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
START condition setup time
Data input hold time
Data input setup time
STOP condition setup time
Output valid from clock
Bus free time
F
CLK
T
HIGH
T
LOW
T
R
T
F
T
HD
:
STA
T
SU
:
STA
T
HD
:
DAT
T
SU
:
DAT
T
SU
:
STO
T
AA
T
BUF
—
4000
4700
—
—
4000
4700
0
250
4000
—
4700
Max.
100
—
—
1000
300
—
—
—
—
—
3500
—
Vcc = 4.5 - 5.5V
FAST MODE
Min.
—
600
1300
—
—
600
600
0
100
600
—
1300
Max.
400
—
—
300
300
—
—
—
—
—
900
—
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 1
Time the bus must be free
before a new transmission
can start
Note 2, CB
≤
100 pF
Note 3
Byte or Page mode
Note 2
Note 2
After this period the first
clock pulse is generated
Only relevant for repeated
START condition
Note 1
Parameter
Symbol
Units
Remarks
Output fall time from V
IH
minimum to V
IL
maximum
Input filter spike suppression
(SDA and SCL pins)
Write cycle time
T
OF
T
SP
T
WR
—
—
—
250
50
10
20 +0.1
CB
—
—
250
50
10
ns
ns
ms
Note 1: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
Note 2: Not 100% tested. CB = total capacitance of one bus line in pF.
Note 3: The combined T
SP
and V
HYS
specifications are due to new Schmitt trigger inputs which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
FIGURE 1-2:
BUS TIMING DATA
T
F
T
HIGH
T
LOW
T
R
SCL
T
SU
:
STA
T
HD
:
STA
SDA
IN
T
SP
T
AA
SDA
OUT
T
AA
T
HD
:
DAT
T
SU
:
DAT
T
SU
:
STO
T
BUF
©
1995 Microchip Technology Inc.
DS20071G-page 3
24LC01B/02B
2.0
FUNCTIONAL DESCRIPTION
3.4
Data Valid (D)
The 24LC01B/02B supports a bidirectional two wire
bus and data transmission protocol. A device that
sends data onto the bus is defined as transmitter, and
a device receiving data as receiver. The bus has to be
controlled by a master device which generates the
serial clock (SCL), controls the bus access, and gener-
ates the START and STOP conditions, while the
24LC01B/02B works as slave. Both master and slave
can operate as transmitter or receiver but the master
device determines which mode is activated.
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last six-
teen will be stored when doing a write operation. When
an overwrite does occur it will replace data in a first in
first out fashion.
3.0
BUS CHARACTERISTICS
The following
bus protocol
has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
defined (see Figure 3-1).
3.5
Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
Note:
The 24LC01B/02B does not generate any
acknowledge bits if an internal program-
ming cycle is in progress.
3.1
Bus not Busy (A)
Both data and clock lines remain HIGH.
3.2
Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition.
All commands must be preceded by a START condi-
tion.
3.3
Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this
case, the slave must leave the data line HIGH to enable
the master to generate the STOP condition.
FIGURE 3-1:
(A)
SCL
(B)
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(D)
(D)
(C)
(A)
SDA
START CONDITION
ADDRESS
DATA ALLOWED
OR
TO CHANGE
ACKNOWLEDGE
VALID
STOP
CONDITION
DS20071G-page 4
©
1995 Microchip Technology Inc.
24LC01B/02B
4.0
4.1
BUS CHARACTERISTICS
Slave Address
5.0
5.1
WRITE OPERATION
Byte Write
The 24LC01B/02B are software-compatible with older
devices such as 24C01A, 24C02A, 24LC01, and
24LC02. A single 24LC02B can be used in place of two
24LC01's, for example, without any modifications to
software. The “chip select” portion of the control byte
becomes a don't care.
After generating a START condition, the bus master
transmits the slave address consisting of a 4-bit device
code (1010) for the 24LC01B/02B, followed by three
don't care bits.
The eighth bit of slave address determines if the master
device wants to read or write to the 24LC01B/02B (see
Figure 4-1).
The 24LC01B/02B monitors the bus for its correspond-
ing slave address all the time. It generates an acknowl-
edge bit if the slave address was true and it is not in a
programming mode.
Operation
Read
Write
Control
Code
1010
1010
Chip
Select
XXX
XXX
R/W
1
0
Following the start signal from the master, the device
code (4 bits), the don't care bits (3 bits), and the R/W
bit which is a logic low is placed onto the bus by the
master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will fol-
low after it has generated an acknowledge bit during
the ninth clock cycle. Therefore the next byte transmit-
ted by the master is the word address and will be writ-
ten into the address pointer of the 24LC01B/02B. After
receiving another acknowledge signal from the
24LC01B/02B the master device will transmit the data
word to be written into the addressed memory location.
The 24LC01B/02B acknowledges again and the mas-
ter generates a stop condition. This initiates the inter-
nal write cycle, and during this time the 24LC01B/02B
will not generate acknowledge signals (see Figure 5-
1).
5.2
Page Write
FIGURE 4-1:
CONTROL BYTE
ALLOCATION
READ/WRITE
START
SLAVE ADDRESS
R/W
A
1
0
1
0
X
X
X
The write control byte, word address and the first data
byte are transmitted to the 24LC01B/02B in the same
way as in a byte write. But instead of generating a stop
condition the master transmits up to eight data bytes to
the 24LC01B/02B which are temporarily stored in the
on-chip page buffer and will be written into the memory
after the master has transmitted a stop condition. After
the receipt of each word, the three lower order address
pointer bits are internally incremented by one. The
higher order five bits of the word address remains con-
stant. If the master should transmit more than eight
words prior to generating the stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the stop condition is received an inter-
nal write cycle will begin (see Figure 8-1).
X = don't care
FIGURE 5-1:
BYTE WRITE
BUS ACTIVITY:
MASTER
SDA LINE
BUS ACTIVITY:
S
T
A
R
T
S
CONTROL
BYTE
WORD
ADDRESS
DATA
S
T
O
P
P
A
C
K
A
C
K
A
C
K
©
1995 Microchip Technology Inc.
DS20071G-page 5
Microcontroller MCU
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