BR24C04F-W datasheet, PDF - EEWORLD Datasheet

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BR24C04F-W: DescriptionI2C BUS compatible serial EEPROM; Categorystorage storage; File Size340KB，13 Pages; ManufacturerROHM Semiconductor; Websitehttps://www.rohm.com/; Environmental Compliance

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BR24C04F-W Overview

I2C BUS compatible serial EEPROM

BR24C04F-W Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Parts packaging code	SOIC
package instruction	LSOP, SOP8,.25
Contacts	8
Reach Compliance Code	unknow
ECCN code	EAR99
Is Samacsys	N
Maximum clock frequency (fCLK)	0.4 MHz
Data retention time - minimum	10
Durability	100000 Write/Erase Cycles
I2C control byte	1010DDMR
JESD-30 code	R-PDSO-G8
JESD-609 code	e2
length	5 mm
memory density	4096 bi
Memory IC Type	EEPROM
memory width	8
Number of functions	1
Number of terminals	8
word count	512 words
character code	512
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	512X8
Package body material	PLASTIC/EPOXY
encapsulated code	LSOP
Encapsulate equivalent code	SOP8,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, LOW PROFILE
Parallel/Serial	SERIAL
Peak Reflow Temperature (Celsius)	260
power supply	3/5 V
Certification status	Not Qualified
Maximum seat height	1.6 mm
Serial bus type	I2C
Maximum standby current	0.000002 A
Maximum slew rate	0.002 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	2.7 V
Nominal supply voltage (Vsup)	3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	TIN COPPER
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	10
width	4.4 mm
write protect	HARDWARE
Base Number Matches	1

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BR24C01A-W / BR24C01AF-W / BR24C01AFJ-W / BR24C01AFV-W / BR24C02-W / BR24C02F-W /

Memory ICs

BR24C02FJ-W / BR24C02FV-W / BR24C04-W / BR24C04F-W / BR24C04FJ-W / BR24C04FV-W

C BUS compatible serial EEPROM

BR24C01A-W / BR24C01AF-W / BR24C01AFJ-W /

BR24C01AFV-W / BR24C02-W / BR24C02F-W /

BR24C02FJ-W / BR24C02FV-W / BR24C04-W /

BR24C04F-W / BR24C04FJ-W / BR24C04FV-W

The BR24C01A-W, BR24C02-W, and BR24C04-W series are 2-wire (I

C BUS type) serial EEPROMs which are

electrically programmable.

∗

C BUS is a registered trademark of Philips.

Applications

VCRs, TVs, printers, car stereos, cordless telephones, short wave radios, programmable DIP switches

Features

1) 128×8bits (1k) serial EEPROM.

(BR24C01A-W / AF-W / AFJ-W / AFV-W)

256×8bits (2k) serial EEPROM.

(BR24C02-W / F-W / FJ-W / FV-W)

512×8bits (4k) serial EEPROM.

(BR24C04-W / F-W / FJ-W / FV-W)

2) Two wire serial interface.

3) Operating voltage range : 2.7V∼5.5V

4) Low current consumption

Active (at 5V) : 1.5mA (Typ.)

Standby (at 5V) : 0.1µA (Typ.)

5) Auto erase and auto complete functions can be used

during write operations.

6) Page write function.

BR24C01A-W / AF-W / AFJ-W / AFV-W : 8 bytes

BR24C02-W / F-W / FJ-W / FV-W : 8 bytes

BR24C04-W / F-W / FJ-W / FV-W : 16 bytes

7) DATA security

Write protect feature

Inhibit to WRITE at low V

8) Noise filters at SCL and SDA pins.

9) Address can be incremented automatically during

read operations.

10) Compact packages.

11) Rewriting possible up to 100,000 times

12) Data can be stored for ten years without corruption.

Absolute maximum ratings

(Ta = 25°C)

Parameter

Applied voltage

Symbol

Limits

−0.3

+6.5

300(SSOP−B8)

Power dissipation

450(SOP8, SOP−J8)

800(DIP8)

Storage temperature

Operating temperature

Input voltage

Tstg

Topr

−

−65

+125

−40

+85

−0.3

+0.3

∗1

∗2

∗3

Unit

°C

∗1

Reduced by 3.0mW for each increase in Ta of 1°C over 25°C.

∗2

Reduced by 4.5mW for each increase in Ta of 1°C over 25°C.

∗3

Reduced by 8.0mW for each increase in Ta of 1°C over 25°C.

BR24C01A-W / BR24C01AF-W / BR24C01AFJ-W / BR24C01AFV-W / BR24C02-W / BR24C02F-W /

Memory ICs

BR24C02FJ-W / BR24C02FV-W / BR24C04-W / BR24C04F-W / BR24C04FJ-W / BR24C04FV-W

(4) Device addressing

– BR24C01A-W / AF-W / AFJ-W / AFV-W, BR24C02-W / F-W / FJ-W / FV-W

1) Make sure the slave address is output from the master immediately after the start condition.

2) The upper four bits of the slave address are used to determine the device type. The device code for this IC is

fixed at “1010”.

3) The next three bits of the slave address (A2, A1, A0 … device address) are used to select the device. This IC

can address up to eight devices on the same bus.

4) The lowermost bit of the slave address (R / W … READ / WRITE) is used to set the write or read mode as follows.

R / W set to 0 … Write

(Random read word address setting is also 0)

R / W set to 1 … Read

1010

R/W

– BR24C04-W / F-W / FJ-W / FV-W

1) Make sure the slave address is output from the master in continuation with the start condition.

2) The upper four bits of the slave address are used to determine the device type. The device code for this IC is

fixed at “1010”.

3) The next two bits of the slave address (A2, A1, … device address) are used to select the device. This IC can

address up to four devices on the same bus.

4) The next bit of the slave address (PS … Page Select) is used to select the page. As shown below, it can write to

or read from any of the 256 words in the two pages in memory.

PS set to 0 … Page 1 (000 to 0FF)

PS set to 1 … Page 2 (100 to 1FF)

5) The lowermost bit of the slave address (R / W … READ / WRITE) is used to set the write or read mode as follows.

R / W set to 0 … Write

(Random read word address setting is also 0)

R / W set to 1 … Read

1010

R/W

(5) Write protect (WP)

When WP pin set to V

(High level), write protect is set by all address. When WP pin set to GND (Low level),

enable to write to all address. Either control this pin or connect to GND (or V

). It is inhibited from being left

unconnected.

(6) ACK signal

The acknowledge signal (ACK signal) is determined by software and is used to indicate whether or not a data transfer

is proceeding normally. The transmitting device, whether the master or slave, opens the bus after an 8-bit data

output (µ-COM when a write or read command of the slave address input ; this IC when reading data).

For the receiving device during the ninth clock cycle, SDA is set to LOW and an acknowledge signal (ACK signal) is

sent to indicate that it received the 8-bit data (this IC when a write command or a read command of the slave address

input,

µ-COM

when a read command data output).

The ICs output a LOW acknowledge signal (ACK signal) after recognizing the start condition and slave address (8

bits).

When data is being write to the ICs, a LOW acknowledge signal (ACK signal) is output after the receipt of each eight

bits of data (word address and write data).

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