Memory Ics
BR24C08 / BR24C08F / BR24C08FJ / BR24C08FV / BR24C16/ BR24C16F /
BR24C16FJ / BR24C16FV / BR24E16 / BR24E16F / BR24E16FJ / BR24E16FV
I
2
C BUS compatible serial EEPROM
BR24C08 / BR24C08F / BR24C08FJ / BR24C08FV /
BR24C16 / BR24C16F / BR24C16FJ / BR24C16FV /
BR24E16 / BR24E16F / BR24E16FJ / BR24E16FV /
The BR24C08, BR24C16 and BR24E16 series are 2-wire (I
2
C BUS type) serial EEPROMs which are electrically
programmable.
∗I
2
C BUS is a registered trademark of Philips.
Features
1) 1k x 8 bits serial EEPROM.
(BR24C08 / F / FJ / FV)
2k x 8 bits serial EEPROM.
(BR24C16 / F / FJ / FV, BR24E16 / F / FJ / FV)
2) Two wire serial interface.
(2Byte Address : BR24E16)
3) Operating voltage range : 2.7V∼5.5V
4) Low current consumption
Active (at 5V) : 2.0mA (Typ.)
Standby (at 5V) : 1.0µA (Typ.)
5) Auto erase and auto complete functions can be used
during write operations.
6) Page write function : 16byte
7) DATA security
Write protect feature
Inhibit to WRITE at low Vcc
8) Noise filters at SCL and SDA pins.
9) Address can be incremented automatically during
read operations.
10) Compact packages.
11) Rewriting possible up to 100,000 times.
12) Data can be stored for ten years without corruption.
Absolute maximum ratings
(Ta=25°C)
Parameter
Supply voltage
Symbol
V
CC
Limits
−0.3
~
+6.5
300(SSOP−B8)
Power dissipation
Pd
∗1
Unit
V
450(SOP8, SOP−J8)
∗2
800(DIP8)
∗3
mW
Storage temperature range
Operating temperature range
Terminal voltage
Tstg
Topr
−
−65
~
+125
−40
~
+85
−0.3
~V
CC
+0.3
°C
°C
V
∗1
Reduced by 3.0mW for each increase in Ta of 1
°C
over
25
°C.
∗2
Reduced by 3.5mW for each increase in Ta of 1
°C
over
25
°C.
∗3
Reduced by 5.0mW for each increase in Ta of 1
°C
over
25
°C.
Recommended operating conditions
(Ta=25°C)
Parameter
Power supply voltage
Input voltage
Symbol
V
CC
V
IN
Limits
2.7~5.5
0~V
CC
Unit
V
V
Memory Ics
Block diagram
BR24C08 / F / FJ / FV
A0
1
10bits
BR24C08 / BR24C08F / BR24C08FJ / BR24C08FV / BR24C16/ BR24C16F /
BR24C16FJ / BR24C16FV / BR24E16 / BR24E16F / BR24E16FJ / BR24E16FV
8kbits EEPROM ARRAY
8bits
8
V
CC
Pin name
V
CC
GND
I/O
−
−
−
I
I
I/O
I
Power supply
Ground (0V)
Function
A1
2
ADDRESS
DECODER
10bits
SLAVE
·
WORD
ADDRESS REGISTER
DATA
REGISTER
7
WP
A0, A1
A2
Out of use. Please connect to GND.
Slave address set
Serial clock input
Slave and word address,
serial data input, serial data output
Wite protect pin
∗
START
STOP
A2
3
CONTROL LOGIC
ACK
6
SCL
SCL
SDA
GND
4
HIGH VOLTAGE GEN.
V
CC
LEVEL DETECT
5
SDA
WP
∗An
open drain output requires a pull-up resistor.
BR24C16 / F / FJ / FV
A0
1
11bits
16kbits EEPROM ARRAY
8bits
8
V
CC
Pin name
V
CC
I/O
−
−
I
I
I/O
I
Power supply
Ground (0V)
Function
A1
2
ADDRESS
DECODER
11bits
SLAVE
·
WORD
ADDRESS REGISTER
DATA
REGISTER
7
WP
GND
A0, A1, A2
SCL
Out of use. Please connect to GND.
Serial clock input
Slave and word address,
serial data input, serial data output
Wite protect pin
∗
START
STOP
A2
3
CONTROL LOGIC
ACK
6
SCL
SDA
WP
GND
4
HIGH VOLTAGE GEN.
V
CC
LEVEL DETECT
5
SDA
∗An
open drain output requires a pull-up resistor.
BR24E16 / F / FJ / FV
A0
1
11bits
16kbits EEPROM ARRAY
8bits
8
V
CC
Pin name
7
WP
I/O
−
−
I
I
I/O
I
Power supply
Ground (0V)
Function
A1
2
ADDRESS
DECODER
11bits
SLAVE
·
WORD
ADDRESS REGISTER
DATA
REGISTER
V
CC
GND
START
STOP
A0, A1, A2
6
ACK
Slave address set
Serial clock input
Slave and word address,
serial data input, serial data output
Wite protect pin
∗
A2
3
CONTROL LOGIC
SCL
SCL
SDA
GND
4
HIGH VOLTAGE GEN.
V
CC
LEVEL DETECT
5
SDA
WP
∗An
open drain output requires a pull-up resistor.
Memory Ics
BR24C08 / BR24C08F / BR24C08FJ / BR24C08FV / BR24C16/ BR24C16F /
BR24C16FJ / BR24C16FV / BR24E16 / BR24E16F / BR24E16FJ / BR24E16FV
Electrical characteristics
DC characteristics (Unless otherwise noted, Ta=−40∼85°C, V
CC
=2.7∼5.5V)
Parameter
"HIGH" input voltage
"LOW" input voltage
"LOW" output voltage
Input leakage current
Output leakage current
operating current
Standby current
Symbol
V
IH
V
IL
V
OL
I
LI
I
LO
I
CC
I
SB
Min.
0.7V
CC
−
−
−1
−1
−
−
Typ.
−
−
−
−
−
−
−
Max.
−
0.3V
CC
0.4
1
1
3.0
3.0
Unit
V
V
V
µA
µA
mA
µA
I
OL
=3.0mA(SDA)
V
IN
=0V
~V
CC
V
OUT
=0V
~V
CC
V
CC
=5.5V,
f
SCL
=400kHz
V
CC
=5.5V,
SDA SCL=V
CC
A0, A1, A2=GND, WP=GND
Conditions
−
−
This product is not designed for protection against radioactive rays.
Operating timing characteristics (Unless otherwise noted, Ta=−40∼85°C, V
CC
=2.7∼5.5V)
Vcc=5V±10%
Parameter
SCL frequency
Dataclock "HIGH" time
Dataclock "LOW" time
SDA / SCL rise time
SDA / SCL fall time
Start condition hold time
Start condition setup time
Input data hold time
Input data setup time
Output data delay time
Output data hold time
Stop condition setup time
Bus open time before start or transfer
Internal write cycle time
Noise erase valid time (SDA/SCL pins)
Symbol
f
SCL
t
HIGH
t
LOW
t
R
t
F
t
HD
: STA
t
SU
: STA
t
HD
: DAT
t
SU
: DAT
t
PD
t
DH
t
SU
: STO
t
BUF
t
WR
t
I
Min.
−
0.6
1.2
−
−
0.6
0.6
0
100
0.1
0.1
0.6
1.2
−
−
Typ.
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
Max.
400
−
−
0.3
0.3
−
−
−
−
0.9
−
−
−
10
0.05
−
4.0
4.7
−
−
4.0
4.7
0
250
0.2
0.2
4.7
4.7
−
−
Vcc=3V±10%
Min.
Typ.
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
Max.
100
−
−
1.0
0.3
−
−
−
−
3.5
−
−
−
10
0.1
Unit
kHz
µs
µs
µs
µs
µs
µs
ns
ns
µs
µs
µs
µs
ms
µs
Memory Ics
Timing charts
BR24C08 / BR24C08F / BR24C08FJ / BR24C08FV / BR24C16/ BR24C16F /
BR24C16FJ / BR24C16FV / BR24E16 / BR24E16F / BR24E16FJ / BR24E16FV
t
R
SCL
t
HD
SDA
(IN)
t
BUF
SDA
(OUT)
t
F
t
HIGH
:
STA
t
SU
:
DAT
t
LOW
t
HD
:
DAT
t
PD
t
DH
SCL
t
SU
SDA
:
STA
t
HD
:
STA
t
SU
:
STO
START BIT
STOP BIT
Data is read on the rising edge of SCL.
Data is output in synchronization with the falling edge of SCL.
Fig.1 Synchronized data input / output timing
SCL
SDA
D0
Write data (n)
ACK
t
WR
STOP CONDITION
START CONDITION
Fig.2 Write cycle timing
Circuit operation
(1) Start condition (recognition of start bit)
Before executing any command, when SCL is HIGH, a start condition (start bit) is required to cause SDA to fall from
HIGH to LOW. This IC is designed to constantly detect whether there is a start condition (start bit) for the SDA and
SCL line, and no commands will be executed unless this condition is satisfied.
(See Fig.1 for the synchronized data input / output timing.)
(2) Stop condition (recognition of stop bit)
To stop any command, a stop condition (stop bit) is required. A stop condition is achieved when SDA goes from LOW
to HIGH while SCL is HIGH. This enables commands to be completed.
(See Fig.1 for the synchronized data input / output timing.)
(3) Precautions concerning write commands
In the WRITE mode, the transferred data is not written to the memory unless the stop bit is executed.
Memory Ics
BR24C08 / BR24C08F / BR24C08FJ / BR24C08FV / BR24C16/ BR24C16F /
BR24C16FJ / BR24C16FV / BR24E16 / BR24E16F / BR24E16FJ / BR24E16FV
(4) Device addressing
BR24C08 / F / FJ / FV
1) Make sure the slave address is output from the master in continuation with the start condition.
2) The upper 4bits of the slave address are used to determine the device type. The device code for this IC is fixed at
“1010”.
3) The next 1bit of the slave address (A2 … device address) are used to select the device. This IC can address up to
two devices on the same bus.
4) The next 2bits (P1, P0 … page select) are used by the master to select four 256 word page of memory.
P1, P0 set to ‘0’ ‘0’
$ $ $ $ $ $ $
1 page (000 ~0FF)
P1, P0 set to ‘0’ ‘1’
$ $ $ $ $ $ $
2 page (100 ~1FF)
P1, P0 set to ‘1’ ‘0’
$ $ $ $ $ $ $
3 page (200 ~2FF)
P1, P0 set to ‘1’ ‘1’
$ $ $ $ $ $ $
4 page (300 ~3FF)
5) The lowermost bit of the slave address (R / W … READ / WRITE) is used to set the write or read mode as follows.
R / W set to 0 … Write
(Random read word address setting is also 0)
R / W set to 1 … Read
1010
A2
P1
P0
R/W
BR24C16 / F / FJ / FV
1) Make sure the slave address is output from the master in continuation with the start condition.
2) The upper 4bits of the slave address are used to determine the device type. The device code for this IC is fixed at
“1010”.
3) The next 3bits (P2, P1, P0 … page select) are used by the master to select four 256 word page of memory.
P2, P1, P0 set to ‘0’ ‘0’ ‘0’$
$ $ $ $ $ $
1 page (000 ~0FF)
P2, P1, P0 set to ‘0’ ‘0’ ‘1’$
$ $ $ $ $ $
2 page (100 ~1FF)
:
:
P2, P1, P0 set to ‘1’ ‘1’ ‘1’$
$ $ $ $ $ $
8 page (700 ~7FF)
4) The lowermost bit of the slave address (R / W … READ / WRITE) is used to set the write or read mode as follows.
R / W set to 0 … Write
(Random read word address setting is also 0)
R / W set to 1 … Read
1010
P2
P1
P0
R/W
BR24E16 / F / FJ / FV
1) Make sure the slave address is output from the master in continuation with the start condition.
2) The upper 4bits of the slave address are used to determine the device type. The device code for this IC is fixed at
“1010”.
3) The next 3bits of the slave address (A2, A1, A0 … device address) are used to select the device. This IC can
address up to eight devices on the same bus.
4) The lowermost bit of the slave address (R / W … READ / WRITE) is used to set the write or read mode as follows.
R / W set to 0 … Write
(Random read word address setting is also 0)
R / W set to 1 … Read
1010
A2
A1
A0
R/W
京公网安备 11010802033920号
EEWORLD
