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74AUP2G07

Description
AUP/ULP/V SERIES, DUAL 1-INPUT NON-INVERT GATE, PDSO6
Categorysemiconductor    logic   
File Size450KB,13 Pages
ManufacturerDiodes
Websitehttp://www.diodes.com/
Download Datasheet Parametric Compare View All

74AUP2G07 Overview

AUP/ULP/V SERIES, DUAL 1-INPUT NON-INVERT GATE, PDSO6

74AUP2G07 Parametric

Parameter NameAttribute value
Number of functions2
Number of terminals6
Maximum operating temperature125 Cel
Minimum operating temperature-40 Cel
Maximum supply/operating voltage3.6 V
Minimum supply/operating voltage0.8000 V
Rated supply voltage3 V
Processing package description1 X 1 MM, GREEN, DFN-6
stateACTIVE
CraftsmanshipCMOS
packaging shapeSQUARE
Package SizeSMALL OUTLINE, VERY THIN PROFILE
surface mountYes
Terminal formNO LEAD
Terminal spacing0.3500 mm
Terminal locationDUAL
Packaging MaterialsPLASTIC/EPOXY
Temperature levelAUTOMOTIVE
seriesAUP/ULP/V
Output characteristicsO-DRN
Logic IC typeNON-INVERT
Number of inputs1
propagation delay TPD25.8 ns
74AUP2G07
DUAL BUFFERS WITH OPEN DRAIN OUTPUTS
Description
The Advanced Ultra Low Power (AUP) CMOS logic family is designed
for low power and extended battery life in portable applications.
The 74AUP2G07 is composed of two buffers with open drain outputs
designed for operation over a power supply range of 0.8V to 3.6V.
The device is fully specified for partial power down applications using
I
OFF
. The I
OFF
circuitry disables the output preventing damaging
Pin Assignments
(Top View)
1A
1
GND
2
2A
3
SOT363
6
1Y
5
Vcc
4
2Y
(Top View)
1A
GND
2A
1
2
3
6
1Y
5
Vcc
4
2Y
NEW PRODUCT
current backflow when the device is powered down. The gates
perform the positive Boolean function:
Y
½
A
X2-DFN1410-6
Features
Advanced Ultra Low Power (AUP) CMOS
Supply Voltage Range from 0.8V to 3.6V
-4mA Output Drive at 3.0V
Low Static Power Consumption
I
CC
< 0.9µA
Low Dynamic Power Consumption
C
PD
= 1.2pF Typical at 3.6V
Schmitt Trigger Action at All Inputs Make the Circuit Tolerant for
Slower Input Rise and Fall Time. The Hysteresis is Typically
250mV at V
CC
= 3.0V
I
OFF
Supports Partial-Power-Down Mode Operation
ESD Protection per JESD 22
Exceeds 200-V Machine Model (A115)
Exceeds 2000-V Human Body Model (A114)
Exceeds 1000-V Charged Device Model (C101)
Latch-Up Exceeds 100mA per JESD 78, Class I
Leadless Packages per JESD30E
DFN1410 denoted as X2-DFN1410-6
DFN1010 denoted as X2-DFN1010-6
DFN0910 denoted as X2-DFN0910-6
Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2)
Halogen and Antimony Free. “Green” Device (Note 3)
(Top View)
1A
GND
2A
1
2
3
6
5
4
1Y
Vcc
2Y
(Top View)
1A
GND
2A
1
2
3
5
4
1Y
Vcc
2Y
X2-DFN1010-6
X2-DFN0910-6
Applications
Suited for Battery and Low Power Needs
Wide array of products such as:
PCs, Networking, Notebooks, Netbooks, PDAs
Tablet Computers, E-readers
Computer Peripherals, Hard Drives, CD/DVD ROM
TV, DVD, DVR, Set-Top Box
Cell Phones, Personal Navigation / GPS
MP3 players, Cameras, Video Recorders
Notes:
1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS) & 2011/65/EU (RoHS 2) compliant.
2. See http://www.diodes.com/quality/lead_free.html for more information about Diodes Incorporated’s definitions of Halogen- and Antimony-free, "Green"
and Lead-free.
3. Halogen- and Antimony-free "Green” products are defined as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl) and
<1000ppm antimony compounds.
74AUP2G07
Document number: DS35511 Rev. 5 - 2
1 of 13
www.diodes.com
November 2014
© Diodes Incorporated

74AUP2G07 Related Products

74AUP2G07 74AUP2G07FW4-7 74AUP2G07FW3-7
Description AUP/ULP/V SERIES, DUAL 1-INPUT NON-INVERT GATE, PDSO6 AUP/ULP/V SERIES, DUAL 1-INPUT NON-INVERT GATE, PDSO6 AUP/ULP/V SERIES, DUAL 1-INPUT NON-INVERT GATE, PDSO6
Number of functions 2 2 2
Number of terminals 6 6 6
Maximum operating temperature 125 Cel 125 Cel 125 Cel
Minimum operating temperature -40 Cel -40 Cel -40 Cel
Maximum supply/operating voltage 3.6 V 3.6 V 3.6 V
Minimum supply/operating voltage 0.8000 V 0.8000 V 0.8000 V
Rated supply voltage 3 V 3 V 3 V
Processing package description 1 X 1 MM, GREEN, DFN-6 1 X 1 MM, GREEN, DFN-6 1 X 1 MM, GREEN, DFN-6
state ACTIVE ACTIVE ACTIVE
Craftsmanship CMOS CMOS CMOS
packaging shape SQUARE SQUARE SQUARE
Package Size SMALL OUTLINE, VERY THIN PROFILE SMALL OUTLINE, VERY THIN PROFILE SMALL OUTLINE, VERY THIN PROFILE
surface mount Yes Yes Yes
Terminal form NO LEAD NO LEAD NO LEAD
Terminal spacing 0.3500 mm 0.3500 mm 0.3500 mm
Terminal location DUAL DUAL DUAL
Packaging Materials PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
Temperature level AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE
series AUP/ULP/V AUP/ULP/V AUP/ULP/V
Output characteristics O-DRN O-DRN O-DRN
Logic IC type NON-INVERT NON-INVERT NON-INVERT
Number of inputs 1 1 1
propagation delay TPD 25.8 ns 25.8 ns 25.8 ns
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