MPC8544CVTANJ datasheet, PDF - EEWORLD Datasheet

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MPC8544CVTANJ: DescriptionMPU POWERQUICC III 783-PBGA; Categorysemiconductor The embedded processor and controller; File Size1MB，120 Pages; ManufacturerFREESCALE (NXP)

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MPC8544CVTANJ Overview

MPU POWERQUICC III 783-PBGA

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Freescale Semiconductor

Technical Data

Document Number: MPC8544EEC

Rev. 3, 11/2009

MPC8544E PowerQUICC™ III

Integrated Processor

Hardware Specifications

MPC8544E Overview

Contents

MPC8544E Overview . . . . . . . . . . . . . . . . . . . . . . . . . 1

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 8

Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 13

Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 16

DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . 17

DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Enhanced Three-Speed Ethernet (eTSEC),

MII Management . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Ethernet Management Interface Electrical

Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Programmable Interrupt Controller . . . . . . . . . . . . . 56

JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

High-Speed Serial Interfaces (HSSI) . . . . . . . . . . . . 65

PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Package Description . . . . . . . . . . . . . . . . . . . . . . . . . 83

Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

System Design Information . . . . . . . . . . . . . . . . . . 107

Device Nomenclature . . . . . . . . . . . . . . . . . . . . . . . 116

Document Revision History . . . . . . . . . . . . . . . . . . 119

This section provides a high-level overview of MPC8544E

features.

Figure 1

shows the major functional units within

the device.

1.1

Key Features

10.

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The following list provides an overview of the device feature

set:

• High-performance 32-bit Book E–enhanced core

built on Power Architecture™ technology:

— 32-Kbyte L1 instruction cache and 32-Kbyte L1

data cache with parity protection. Caches can be

locked entirely or on a per-line basis, with

separate locking for instructions and data.

— Signal-processing engine (SPE) APU (auxiliary

processing unit). Provides an extensive

instruction set for vector (64-bit) integer and

fractional operations. These instructions use both

the upper and lower words of the 64-bit GPRs as

they are defined by the SPE APU.

MPC8544E Overview

— Double-precision floating-point APU. Provides an instruction set for double-precision (64-bit)

floating-point instructions that use the 64-bit GPRs.

— 36-bit real addressing

— Embedded vector and scalar single-precision floating-point APUs. Provide an instruction set

for single-precision (32-bit) floating-point instructions.

— Memory management unit (MMU). Especially designed for embedded applications. Supports

4-Kbyte–4-Gbyte page sizes.

— Enhanced hardware and software debug support

— Performance monitor facility that is similar to, but separate from, the device performance

monitor

The e500 defines features that are not implemented on this device. It also generally defines some features

that this device implements more specifically. An understanding of these differences can be critical to

ensure proper operations.

• 256-Kbyte L2 cache/SRAM

— Flexible configuration

— Full ECC support on 64-bit boundary in both cache and SRAM modes

— Cache mode supports instruction caching, data caching, or both.

— External masters can force data to be allocated into the cache through programmed memory

ranges or special transaction types (stashing).

– 1, 2, or 4 ways can be configured for stashing only.

— Eight-way set-associative cache organization (32-byte cache lines)

— Supports locking entire cache or selected lines. Individual line locks are set and cleared through

Book E instructions or by externally mastered transactions.

— Global locking and flash clearing done through writes to L2 configuration registers

— Instruction and data locks can be flash cleared separately.

— SRAM features include the following:

– I/O devices access SRAM regions by marking transactions as snoopable (global).

– Regions can reside at any aligned location in the memory map.

– Byte-accessible ECC is protected using read-modify-write transaction accesses for

smaller-than-cache-line accesses.

• Address translation and mapping unit (ATMU)

— Eight local access windows define mapping within local 36-bit address space.

— Inbound and outbound ATMUs map to larger external address spaces.

– Three inbound windows plus a configuration window on PCI and PCI Express

– Four outbound windows plus default translation for PCI and PCI Express

• DDR/DDR2 memory controller

— Programmable timing supporting DDR and DDR2 SDRAM

— 64-bit data interface

MPC8544E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3

Freescale Semiconductor

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