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5962-9458506H4A

Description
EEPROM Module, 128KX32, 120ns, Parallel, CMOS, 1.075 INCH, HIP-66
Categorystorage    storage   
File Size741KB,43 Pages
ManufacturerMicrosemi
Websitehttps://www.microsemi.com
Download Datasheet Parametric View All

5962-9458506H4A Overview

EEPROM Module, 128KX32, 120ns, Parallel, CMOS, 1.075 INCH, HIP-66

5962-9458506H4A Parametric

Parameter NameAttribute value
Objectid1902860630
package instruction1.075 INCH, HIP-66
Reach Compliance Codeunknown
Maximum access time120 ns
Other featuresUSER CONFIGURABLE AS 512K X 8
Spare memory width16
Data pollingYES
JESD-30 codeS-XHIP-P66
JESD-609 codee0
length27.305 mm
memory density4194304 bit
Memory IC TypeEEPROM MODULE
memory width32
Number of functions1
Number of terminals66
word count131072 words
character code128000
Operating modeASYNCHRONOUS
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
organize128KX32
Package body materialUNSPECIFIED
encapsulated codeHIP
Encapsulate equivalent codePGA66,11X11
Package shapeSQUARE
Package formIN-LINE
page size128 words
Parallel/SerialPARALLEL
power supply5 V
Programming voltage5 V
Certification statusNot Qualified
Filter levelMIL-STD-883
Maximum seat height4.6 mm
Maximum standby current0.005 A
Maximum slew rate0.25 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelMILITARY
Terminal surfaceTIN LEAD
Terminal formPIN/PEG
Terminal pitch2.54 mm
Terminal locationHEX
switch bitNO
width27.305 mm
Maximum write cycle time (tWC)10 ms
write protectSOFTWARE
REVISIONS
LTR
E
DESCRIPTION
Added device type 06 for vendor cages 54230 and 88379. Added
vendor cage 0EU86 for device types 01 through 06. Figure 1,
changed case outline M to reflect package is available in either a
single or dual cavity. -sld
Added case outline 9.
Added device types 07, 08, and 09 for vendor cage 0EU86. Made
changes to table I to include the addition of device types 07, 08, and
09. Added a min limit to the table I for the I
LI
, and the I
LO
tests. Made
changes to Figures 2, 3, 4, 5, 6, and 8. -sld
Added case outline Z. Updated paragraph 1.2.4, 1.3, figures 1, 2,
and 8. -sld
Added case outline B. Added note to paragraph 1.2.4. -sld
Updated drawing paragraphs. -sld
Paragraph 1.2.4 Case outline M: Correct case outline M package
style from “single/dual” to “dual”. Paragraph 1.2.4 footnote 1/: Delete
“(single cavity)” and “Case outline A can be used if longer leads are
necessary”. Figure 1 case outline M: Correct figure 1 to reflect dual
cavity quad flatpack only for case outline M. -gc
DATE (YR-MO-DA)
99-05-14
APPROVED
K. A. Cottongim
F
G
00-04-06
02-01-31
Raymond Monnin
Raymond Monnin
H
J
K
L
02-06-04
03-10-06
12-04-16
12-08-16
Raymond Monnin
Raymond Monnin
Charles F. Saffle
Charles F. Saffle
REV
SHEET
REV
SHEET
REV STATUS
OF SHEETS
PMIC N/A
L
35
L
15
L
36
L
16
L
17
L
18
REV
SHEET
PREPARED BY
Gary Zahn
CHECKED BY
Michael C. Jones
L
19
L
20
L
21
L
1
L
22
L
2
L
23
L
3
L
24
L
4
L
25
L
5
L
26
L
6
L
27
L
7
L
28
L
8
L
29
L
9
L
30
L
10
L
31
L
11
L
32
L
12
L
33
L
13
L
34
L
14
STANDARD
MICROCIRCUIT
DRAWING
THIS DRAWING IS
AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
AMSC N/A
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
http://www.landandmaritime.dla.mil/
APPROVED BY
Kendall A. Cottongim
MICROCIRCUIT, HYBRID, MEMORY,
DIGITAL, 128K x 32-BIT, ELECTRICALLY
ERASABLE/PROGRAMMABLE READ ONLY
MEMORY
DRAWING APPROVAL DATE
94-08-02
REVISION LEVEL
L
SIZE
A
SHEET
CAGE CODE
67268
1 OF
36
5962-94585
DSCC FORM 2233
APR 97
5962-E441-12
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