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to offer the product to new and existing customers as part of the Infineon product
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Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
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S26KL512S/S26KS512S
S26KL256S/S26KS256S
S26KL128S/S26KS128S
512 Mb (64 MB)/256 Mb (32 MB)/
128 Mb (16 MB), 1.8V/3.0V
HyperFlash™ Family
Features
■
3.0V I/O, 11 bus signals
❐
Single ended clock
1.8V I/O, 12 bus signals
❐
Differential clock (CK, CK#)
Chip Select (CS#)
8-bit data bus (DQ[7:0])
Read-Write Data Strobe (RWDS)
❐
HyperFlash™ memories use RWDS only as a Read Data
Strobe
Up to 333 MBps sustained read throughput
DDR – two data transfers per clock
166-MHz clock rate (333 MBps) at 1.8V V
CC
100-MHz clock rate (200 MBps) at 3.0V V
CC
96-ns initial random read access time
❐
Initial random access read latency: 5 to 16 clock cycles
Sequential burst transactions
■
■
■
■
■
■
■
■
■
■
■
Configurable Burst Characteristics
❐
Wrapped burst lengths:
• 16 bytes (8 clocks)
• 32 bytes (16 clocks)
• 64 bytes (32 clocks)
❐
Linear burst
❐
Hybrid option: one wrapped burst followed by linear burst
❐
Wrapped or linear burst type selected in each transaction
❐
Configurable output drive strength
Low Power Modes
❐
Active Clock Stop During Read: 12 mA, no wake-up required
❐
Standby: 25 µA (typical), no wake-up required
❐
Deep Power-Down: 8 µA (typical)
• 300 µs wake-up required
INT# output to generate external interrupt
❐
Busy to Ready Transition
❐
ECC detection
RSTO# output to generate system level power-on reset
❐
User configurable RSTO# Low period
512-byte Program Buffer
Sector Erase
❐
Uniform 256-KB sectors
❐
Optional Eight 4-KB Parameter Sectors (32 KB total)
Advanced Sector Protection
❐
Volatile and Nonvolatile protection methods for each sector
Separate 1024-byte one-time program array
Operating Temperature
❐
Industrial (–40°C to +85°C)
❐
Industrial Plus (–40°C to +105°C)
❐
Extended (–40°C to +125°C)
❐
Automotive, AEC-Q100 Grade 3 (–40°C to +85°C)
❐
Automotive, AEC-Q100 Grade 2 (–40°C to +105°C)
❐
Automotive, AEC-Q100 Grade 1 (–40°C to +125°C)
ISO/TS16949 and AEC Q100 Certified
Endurance
❐
100,000 program/erase cycles
Retention
❐
20 year data retention
Erase and Program Current
❐
Max Peak
100 mA
Packaging Options
❐
24-Ball FBGA
Additional Features
❐
ECC 1-bit correction, 2-bit detection
❐
CRC
Cypress Semiconductor Corporation
Document Number: 001-99198 Rev. *M
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised June 12, 2019
S26KL512S/S26KS512S
S26KL256S/S26KS256S
S26KL128S/S26KS128S
Performance Summary
Read Access Timings
Maximum Clock Rate at 1.8V V
CC
/V
CC
Q
Maximum Clock Rate at 3.0V V
CC
/V
CC
Q
Maximum Access Time, (t
ACC
)
Maximum CS# Access Time to First Word @ 166 MHz
Typical Program / Erase Times
Single Word Programming (2B = 16b)
Write Buffer Programming (512B = 4096b)
Sector Erase Time (256 KB = 2 Mb)
Typical Current Consumption
Burst Read (Continuous Read at 166 MHz)
Power-On Reset
Sector Erase Current
Write Buffer Programming Current
Standby (CS# = High)
Deep Power-Down (CS# = High, 85°C)
80 mA
80 mA
60 mA
60 mA
25 µA
30 µA (512 Mb)
4 µA (all other densities)
500 µs (~4 KBps)
475 µs (~1 MBps)
930 ms (~282 KBps)
166 MHz
100 MHz
96 ns
118 ns
Document Number: 001-99198 Rev. *M
Page 2 of 101
S26KL512S/S26KS512S
S26KL256S/S26KS256S
S26KL128S/S26KS128S
Contents
1.
1.1
1.2
2.
2.1
3.
4.
4.1
4.2
4.3
4.4
5.
5.1
5.2
6.
6.1
6.2
6.3
7.
7.1
7.2
General Description....................................................
4
DDR Center Aligned Read Strobe
Functionality (DCARS) ................................................. 6
Error Detection and Correction Functionality................ 6
Connection Diagram...................................................
9
FBGA 24-Ball 5 x 5 Array Footprint .............................. 9
Signal Description
.................................................... 10
HyperBus Protocol
...................................................
Command / Address Bit Assignments ........................
Read Operations ........................................................
HyperFlash Read with DCARS Timing.......................
Write Operations ........................................................
11
11
12
15
16
9.1
9.2
10.
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
Endurance ................................................................... 74
Data Retention ............................................................ 74
Electrical Specifications............................................
75
Absolute Maximum Ratings......................................... 75
Thermal Impedance .................................................... 76
Latchup Characteristics............................................... 76
Operating Ranges ....................................................... 76
DC Characteristics (CMOS Compatible) ..................... 77
Power-Up and Power-Down........................................ 79
Power-Off with Hardware Data Protection .................. 83
Power Conservation Modes ........................................ 83
Hardware Interface
Address Space Maps
................................................ 18
Flash Memory Array ................................................... 19
Device ID and CFI (ID-CFI) ASO................................ 21
Embedded Operations..............................................
Embedded Algorithm Controller (EAC).......................
Program and Erase Summary ....................................
Data Protection...........................................................
23
23
24
52
11. Timing Specifications................................................
85
11.1 AC Test Conditions ..................................................... 85
11.2 AC Characteristics....................................................... 86
12.
13.
13.1
13.2
13.3
Embedded Algorithm Performance..........................
91
Ordering Information
................................................. 92
Ordering Part Numbers ............................................... 92
Valid Combinations — Standard ................................. 93
Valid Combinations — Automotive Grade
/ AEC-Q100 ................................................................. 95
Device ID and Common Flash Interface
(ID-CFI) ASO Map
...................................................... 62
Device ID and Common Flash Interface
(ID-CFI) ASO Map — Standard.................................. 62
Device ID and Common Flash Interface
(ID-CFI) ASO Map — Automotive Grade
/ AEC-Q100 ................................................................ 67
Software Interface Reference
.................................. 68
Command Summary................................................... 68
Data Integrity
............................................................. 74
14. Physical Interface
...................................................... 97
14.1 Physical Diagram ........................................................ 97
15. Document History Page
............................................ 98
Sales, Solutions, and Legal Information .........................101
Worldwide Sales and Design Support ......................... 101
Products ...................................................................... 101
PSoC® Solutions ........................................................ 101
Cypress Developer Community ................................... 101
Technical Support ....................................................... 101
8.
8.1
9.
Document Number: 001-99198 Rev. *M
Page 3 of 101
S26KL512S/S26KS512S
S26KL256S/S26KS256S
S26KL128S/S26KS128S
1.
General Description
The Cypress HyperFlash family of products are high-speed CMOS, MirrorBit
NOR flash devices with the HyperBus low signal
count DDR interface, that achieves high speed read throughput. The DDR protocol transfers two data bytes per clock cycle on the
data (DQ) signals. A read or write access for the HyperFlash consists of a series of 16-bit wide, one clock cycle data transfers at the
internal HyperFlash core and two corresponding 8-bit wide, one-half-clock-cycle data transfers on the DQ signals.
Both data and command/address information are transferred in DDR fashion over the 8-bit data bus. The clock input signals are
used for signal capture by the HyperFlash device when receiving command/address/data information on the DQ signals. The Read
Data Strobe (RWDS) is an output from the HyperFlash device that indicates when data is being transferred from the memory to the
host. RWDS is referenced to the rising and falling edges of CK during the data transfer portion of read operations.
Command/address/write-data values are center aligned with the clock edges and read-data values are edge aligned with the
transitions of RWDS.
Read and write operations to the HyperFlash device are burst oriented. Read transactions can be specified to use either a wrapped
or linear burst. During wrapped operation, accesses start at a selected location and continue for a configured number of locations in
a group wrap sequence. During linear operation accesses start at a selected location and continue in a sequential manner until the
read operation is terminated, when CS# returns HIGH. Write transactions transfer one or more16-bit values.
Figure 1. Logic Block Diagram
Mandatory Signals
CS#
CK
CK#
DQ[7:0]
RWDS
Optional Signals
C
O
M
M
A
N
D
D
E
C
O
D
E
R
CONTROL
LOGIC
X
ADDR
RESET#
RSTO#
INT#
PSC
PSC#
X
X
X
X
D
D
D E
D E
E
E CC
C D
CD
D
D EE
E
E RR
R S
R S
S
S
Memory
Memory
Memory
Array
MIRRORBIT
Array
Array
MEMORY ARRAY
Sense Amplifiers
Sense Amplifiers
Sense Amplifiers
SENSE AMPLIFIERS
Y DECODERS
Data Latch
ADDRESS
REGISTER
RWDS
GENERATOR
Y
ADDR
The HyperFlash family consists of multiple densities, 1.8V/3.0V core and I/O, nonvolatile, synchronous flash memory devices. These
devices have an 8-bit (1-byte) wide DDR data bus and use only word-wide (16-bit data) address boundaries. Read operations
provide 16 bits of data during each clock cycle (8 bits on each clock edge). Write operations take 16 bits of data from each clock
cycle (8 bits on each clock edge).
Each random read accesses a 32-byte length and aligned set of data called a page. Each page consists of a pair of 16-byte aligned
groups of array data called half-pages. Half-pages are aligned on 16-byte address boundaries. A read access requires two clock
cycles to define the target half-page address and the burst type, then an additional initial latency. During the initial latency period the
third clock cycle will specify the starting address within the target half-page. After the initial data value has been output, additional
data can be read from the Page on subsequent clock cycles in either a wrapped or linear manner. When configured in linear burst
mode, while a page is being burst out, the device will automatically fetch the next sequential page from the MirrorBit flash memory
array. This simultaneous burst output while fetching from the array allows for a linear sequential burst operation that can provide a
sustained output of 333 MBps data rate [1-byte
(8-bit data bus) * 2 (Data on both clock edges) * 166 MHz = 333 MBps].
Document Number: 001-99198 Rev. *M
Page 4 of 101
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