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5962-8959823MNC

Description
Standard SRAM, 128KX8, 100ns, CMOS, CQCC32
Categorystorage    storage   
File Size441KB,91 Pages
ManufacturerLOGIC Devices
Websitehttp://www.logicdevices.com/
Download Datasheet Parametric View All

5962-8959823MNC Overview

Standard SRAM, 128KX8, 100ns, CMOS, CQCC32

5962-8959823MNC Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
Objectid1516181155
package instructionQCCN, LCC32,.45X.7
Reach Compliance Codeunknown
ECCN code3A001.A.2.C
Maximum access time100 ns
I/O typeCOMMON
JESD-30 codeR-XQCC-N32
JESD-609 codee4
memory density1048576 bit
Memory IC TypeSTANDARD SRAM
memory width8
Humidity sensitivity level3
Number of terminals32
word count131072 words
character code128000
Operating modeASYNCHRONOUS
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
organize128KX8
Output characteristics3-STATE
Package body materialCERAMIC
encapsulated codeQCCN
Encapsulate equivalent codeLCC32,.45X.7
Package shapeRECTANGULAR
Package formCHIP CARRIER
Parallel/SerialPARALLEL
power supply5 V
Certification statusNot Qualified
Filter level38535Q/M;38534H;883B
Maximum standby current0.01 A
Minimum standby current4.5 V
Maximum slew rate0.11 mA
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal surfaceGold (Au)
Terminal formNO LEAD
Terminal pitch1.27 mm
Terminal locationQUAD
REVISIONS
LTR
H
DESCRIPTION
Add device type 41. Make corrections to case outline N, dimension b.
Add vendor CAGE 65786 as source of supply for device type 41.
Update boilerplate. Editorial changes throughout.
Add device types 42, 43, 44, 45, and 46. Editorial changes to pages
1, 3, 7-15. Update boilerplate. ksr
Added provisions to accommodate radiation-hardened devices.
Added device type 47 to drawing. glg
Corrected case outline 8 Figure 1 to show correct numbering of
terminals. Corrected Figure 2 Terminal connections. Corrected the
case outline Y Figure 1 to show the proper distance of E and E1.
Added note to Case outline Y Figure 1, to allow for bottom brazed
package as an alternative style to the side brazed package . Update
boilerplate. Editorial changes throughout. ksr
Changed the minimum value for the Q dimension on package T from
0.026 to 0.020 and removed footnote 12. Editorial changes
throughout.. ksr
Added device type 48 to drawing. ksr
Corrected typo on Figure 4 (Read Cycle). ksr
Vendor requested change in capacitance in Table I for devices 39 and
40 from 5 pF to 8 pF. ksr
DATE (YR-MO-DA)
97-03-26
APPROVED
Raymond Monnin
J
K
L
98-03-03
00-03-01
00-12-08
Raymond Monnin
Raymond Monnin
Raymond Monnin
M
02-12-19
Raymond Monnin
N
P
R
03-08-12
05-08-16
06-02-13
Raymond Monnin
Raymond Monnin
Raymond Monnin
REV
SHEET
REV
SHEET
REV STATUS
OF SHEETS
PMIC N/A
R
35
R
15
R
36
R
16
R
37
R
17
R
38
R
18
REV
R
39
R
19
R
40
R
20
R
41
R
21
R
1
R
42
R
22
R
2
R
43
R
23
R
3
R
44
R
24
R
4
R
45
R
25
R
5
R
46
R
26
R
6
R
47
R
27
R
7
R
48
R
28
R
8
R
49
R
29
R
9
R
50
R
30
R
10
R
51
R
31
R
11
R
52
R
32
R
12
R
33
R
13
R
34
R
14
SHEET
PREPARED BY
Kenneth S. Rice
CHECKED BY
Raymond Monnin
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
http://www.dscc.dla.mil
STANDARD
MICROCIRCUIT
DRAWING
THIS DRAWING IS
AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
AMSC N/A
APPROVED BY
Michael A. Frye
DRAWING APPROVAL DATE
89-04-21
REVISION LEVEL
R
MICROCIRCUIT, MEMORY, DIGITAL,
CMOS, 128K X 8 STATIC RANDOM
ACCESS MEMORY (SRAM) LOW POWER,
MONOLITHIC SILICON
SIZE
A
SHEET
CAGE CODE
67268
1 OF
52
5962-89598
5962-E261-06
DSCC FORM 2233
APR 97
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