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BS616UV1610FC

Description
Ultra Low Power/Voltage CMOS SRAM 1M X 16 bit
File Size216KB,10 Pages
ManufacturerBSI
Websitehttp://www.brilliancesemi.com/
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BS616UV1610FC Overview

Ultra Low Power/Voltage CMOS SRAM 1M X 16 bit

BSI
FEATURES
Ultra Low Power/Voltage CMOS SRAM
1M X 16 bit
BS616UV1610
DESCRIPTION
The BS616UV1610 is a high performance, ultra low power CMOS Static
Random Access Memory organized as 1,048,576 words by 16 bits and
operates from a wide range of 1.8V to 2.3V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 1.2uA and maximum access time of 70/100ns in 2V operation.
Easy memory expansion is provided by an active LOW chip enable(CE1),
active HIGH chip enable (CE2), active LOW output enable(OE) and
three-state output drivers.
The BS616UV1610 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616UV1610 is available in 48-pin BGA package.
• Ultra low operation voltage : 1.8 ~ 2.3V
• Ultra low power consumption :
Vcc = 2.0V C-grade: 25mA (Max.) operating current
I-grade : 30mA (Max.) operating current
1.2uA (Typ.) CMOS standby current
• High speed access time :
-70
70ns (Max.) at Vcc=2V
-10
100ns (Max.) at Vcc=2V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE2,CE1 and OE options
• I/O Configuration x8/x16 selectable by LB and UB pin
PRODUCT FAMILY
SPEED
PRODUCT FAMILY
OPERATING
TEMPERATURE
Vcc
RANGE
(ns)
Vcc=2V
POWER DISSIPATION
STANDBY
Operating
(I
CCSB1
, Max)
(I
CC
, Max)
PKG TYPE
Vcc=2V
30uA
40uA
Vcc=2V
25mA
30mA
BGA
-
BGA
-
BGA
-
BGA
-
48
-
0810
48
-
0912
48
-
0810
48
-
0912
BS616UV1610BC
O
O
+0 C to +70
C
1.8 ~ 2.3V
BS616UV1610FC
BS616UV1610BI
O
O
-
40 C to +85 C 1.8 ~ 2.3V
BS616UV1610FI
70 / 100
70 / 100
PIN CONFIGURATIONS
1
A
B
C
D
E
F
G
H
LB
D8
D9
2
OE
UB
D10
D11
D12
D13
NC
.
A8
3
A0
A3
A5
A17
VSS
A14
A12
A9
4
A1
A4
A6
A7
A16
A15
A13
A10
5
A2
CE1
D1
D3
D4
D5
WE
A11
6
CE2
D0
D2
BLOCK DIAGRAM
A4
A3
A2
A1
A0
A17
A16
A15
A14
A13
A12
Address
Input
Buffer
22
Row
Decoder
2048
Memory Array
2048 x 8192
8192
D0
16
Data
Input
Buffer
16
Column I/O
VSS
VCC
D14
D15
A18
VCC
VSS
D6
D7
A19
.
.
.
.
.
D15
CE2
CE1
WE
OE
UB
LB
Vcc
Gnd
.
.
.
.
Write Driver
Sense Amp
512
Column Decoder
16
Data
Output
16
Buffer
18
Control
Address Input Buffer
A11A10 A9 A8 A7 A6 A5 A18 A19
48-Ball CSP top View
Brilliance Semiconductor Inc
. reserves the right to modify document contents without notice.
R0201-BS616UV1610
1
Revision 2.2
April 2001

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