Output enable (OE:P type) or Stanby (ST:S Type) function allow more low
current consumption.
Actual size
Specifications (characteristics)
Item
Symbol
Specifications
Output frequency range
f
O
Max. supply voltage
V
DD-
GND
Power source
Operating voltage
V
DD
voltage
Storage temperature
T
STG
Temperature
Operating temperature
T
OPR
range
Frequency stability
Current consumption
Output disable current
Standby current
Duty
CMOS level
TTL level
∆f/f0
I
OP
I
OE
I
ST
tw/t
V
OH
Output voltage
V
OL
Output load condition (fan out)
Output enable
CMOS level
disable input voltage
TTL level
CMOS level
CL
V
IH
V
IL
t
TLH
Output rise time
TTL level
CMOS level
Output fall time
TTL level
t
THL
t
OSC
fa
S.R.
Oscillation start up time
Aging
Shock resistance
SG-645PHG
SG-645PCG/SCG
2.5000 MHz to 33.0000 MHz
-0.5 V to +7.0 V
4.5 V to 5.5 V
2.7 V to 3.6 V
-55
°C
to +125
°C
-40
°C
to +85
°C
B :
±50
x 10
-6
C :
±100
x 10
-6
M :
±100
x 10
-6
25 mA Max.
12 mA Max.
20 mA Max.
10 mA Max.
—
50
µA
Max.
—
45 % to 55 %
40 % to 60 %
—
2.4 V Min.
—
V
DD
-0.4 V Min.
—
V
DD
-0.4 V Min.
—
—
0.4 V Max.
0.4 V Max.
—
25 pF
2.0 V Min.
70 % V
DD
Min.
0.8 V Max.
20 % V
DD
Max.
—
3.4 ns Max.
4.0 ns Max.
1.2 ns Max.
—
—
2.4 ns Max.
—
—
—
3.4 ns Max.
4.0 ns Max.
1.2 ns Max.
—
—
2.4 ns Max.
—
—
12 ms Max.
±5
x 10
-6
Max.
±20
x 10
-6
SG-645PTG
Remarks
Refer to page 31. "Frequency range"
Stored as bare product after unpacking
Refer to page 31. "Frequency range"
-20
°C
to +70
°C
-40
°C
to +85
°C
No load condition
OE=GND (P∗G)
ST=GND (SCG)
50 % V
DD
, CL = 25 pF
1.4 V Level, CL = 25 pF
I
OH
= -8 mA
I
OH
= -16 mA
I
OL
= 8 mA
I
OL
= 16 mA
OE,ST
OE,ST
20 % to 80 % V
DD
, CL
≤
25 pF
0.8 V to 2.0 V CL
≤
25 pF
0.4 V to 2.4 V CL
≤
25 pF
80 % to 20 % V
DD
CL
≤
25 pF
2.0 V to 0.8 V CL
≤
25 pF
2.4 V to 0.4 V CL
≤
25 pF
Time at minimum operating voltage to be 0 s
Ta=+25
°C,
VDD = 5.5 V / 3.3 V, First year
Three drops on a hard board from 750 mm or
excitation test with 29400 m/s2 x 0.3 ms x 1/2
sine wave in 3 directions
Note: • Unless otherwise stated, characteristics (specifications) shown in the above table are based on the rated operating temperature and voltage condition.
• External by-pass capacitor is recommended.
Standard output frequency
2.5
3.375
3.579545
3.6864
3.6873625
3.75
3.84
4.0
4.096
3.072
3.125
5.0
5.625
6.144
6.25
6.75
7.15909
7.3728
7.374725
7.5
7.68
8.0
8.192
10.0
11.25
12.288
12.5
13.5
14.31818
14.7456
14.74945
15.0
15.36
16.0
16.384
20.0
22.5
24.576
25.0
27.0
28.63636
29.4912
29.4989
30.0
30.72
32.0
32.768
2.8125
External dimensions
7.1±0.2
(Unit: mm)
Recommended soldering pattern
(Unit: mm)
#4
#3
E 135.00C
PCW0245A
#1
#2
5.3
Max.
NO.
Pin terminal
1 OE or ST
2
GND
3
OUT
4
V
DD
4.6±0.2
1.8
1.5
Max.
0.4
5.08
0
Min.
(0.75)
(0.75)
Note.
OE Pin (PT, PH, PC, PTW, PHW, PCW)
OE pin - "H" or "open" : Specified frequency output.
OE pin - "L" : Output is high impedance.
ST pin (PT, PH, PC, PTW, PHW,PCW)
ST pin - "H" or "open" : Specified frequency output.
ST pin - "L" : Output is low level (weak pull-down), oscillation stops.
4.2
5.08
39
Metal may be exposed on the top or bottom of this product. This won't affect any quality, reliability or electrical spec.
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FPGA/CPLD
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