ADVANCED INFORMATION
MX29F004CT/CB
4M-BIT [512KX8] CMOS FLASH MEMORY
FEATURES
• 524,288 x 8 only
• Single power supply operation
- 5.0V only operation for read, erase and program op-
eration
• Fully compatible with MX29F004T/B device
• Fast access time: 70/90/120ns
• Low power consumption
- 30mA maximum active current (5MHz)
- 1uA typical standby current
• Command register architecture
- Byte Programming (9us typical)
- Sector Erase
(Sector structure:16KB/8KB/8KB/32KB and 64KBx7)
• Auto Erase (chip & sector) and Auto Program
- Automatically erase any combination of sectors with
Erase Suspend capability.
- Automatically program and verify data at specified
address
• Erase suspend/Erase Resume
- Suspends an erase operation to read data from, or
program data to, another sector that is not being
erased, then resumes the erase.
Status Reply
- Data# Polling & Toggle bit for detection of program
and erase cycle completion.
Chip protect/unprotect for 5V only system or 5V/12V
system.
100,000 minimum erase/program cycles
Latch-up protected to 100mA from -1V to VCC+1V
Boot Code Sector Architecture
- T = Top Boot Sector
- B = Bottom Boot Sector
Low VCC write inhibit is equal to or less than 3.2V
Package type:
- 32-pin PLCC, TSOP or PDIP
Compatibility with JEDEC standard
- Pinout and software compatible with single-power
supply Flash
20 years data retention
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GENERAL DESCRIPTION
The MX29F004CT/CB is a 4-mega bit Flash memory
organized as 512K bytes of 8 bits. MXIC's Flash memo-
ries offer the most cost-effective and reliable read/write
non-volatile random access memory. The MX29F004CT/
CB is packaged in 32-pin PLCC, TSOP, PDIP. It is de-
signed to be reprogrammed and erased in system or in
standard EPROM programmers.
The standard MX29F004CT/CB offers access time as
fast as 70ns, allowing operation of high-speed micropro-
cessors without wait states. To eliminate bus conten-
tion, the MX29F004CT/CB has separate chip enable
(CE#) and output enable (OE#) controls.
MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX29F004CT/CB uses a command register to manage
this functionality. The command register allows for 100%
TTL level control inputs and fixed power supply levels
during erase and programming, while maintaining maxi-
mum EPROM compatibility.
MXIC Flash technology reliably stores memory con-
tents even after 100,000 erase and program cycles.
The MXIC cell is designed to optimize the erase
and programming mechanisms. In addition, the
combination of advanced tunnel oxide processing
and low internal electric fields for erase and pro-
gram operations produces reliable cycling. The
MX29F004CT/CB uses a 5.0V±10% VCC supply to
perform the High Reliability Erase and auto Pro-
gram/Erase algorithms.
The highest degree of latch-up protection is
achieved with MXIC's proprietary non-epi process.
Latch-up protection is proved for stresses up to 100
milliamps on address and data pin from -1V to VCC
+ 1V.
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MX29F004CT/CB
AUTOMATIC PROGRAMMING
The MX29F004CT/CB is byte programmable using the
Automatic Programming algorithm. The Automatic Pro-
gramming algorithm makes the external system do not
need to have time out sequence nor to verify the data
programmed. The typical chip programming time at room
temperature of the MX29F004CT/CB is less than 4.5
seconds.
AUTOMATIC ERASE ALGORITHM
MXIC's Automatic Erase algorithm requires the user to
write commands to the command register using stan-
dard microprocessor write timings. The device will auto-
matically pre-program and verification the entire array.
Then the device automatically times the erase pulse width,
provides the erase verify, and counts the number of se-
quences. A status bit toggling between consecutive read
cycles provides feedback to the user as to the status of
the programming operation.
Register contents serve as inputs to an internal state-
machine which controls the erase and programming cir-
cuitry. During write cycles, the command register inter-
nally latches address and data needed for the program-
ming and erase operations. During a system write cycle,
addresses are latched on the falling edge of WE# or
CE#, whichever happens later, and data are latched on
the rising edge of WE# or CE#, whichever happens first.
MXIC's Flash technology combines years of EPROM
experience to produce the highest levels of quality, reli-
ability, and cost effectiveness. The MX29F004CT/CB
electrically erases all bits simultaneously using Fowler-
tunneling. The bytes are programmed by using the
EPROM programming mechanism of hot electron injec-
tion.
During a program cycle, the state-machine will control
the program sequences and command register will not
respond to any command set. During a Sector Erase
cycle, the command register will only respond to Erase
Suspend command. After Erase Suspend is completed,
the device stays in read mode. After the state machine
has completed its task, it will allow the command regis-
ter to respond to its full command set.
AUTOMATIC CHIP ERASE
The entire chip is bulk erased using 10 ms erase pulses
according to MXIC's Automatic Chip Erase algorithm.
Typical erasure at room temperature is accomplished in
less than 4 second. The Automatic Erase algorithm au-
tomatically programs the entire array prior to electrical
erase. The timing and verification of electrical erase are
controlled internally within the device.
AUTOMATIC SECTOR ERASE
The MX29F004CT/CB is sector(s) erasable using MXIC's
Auto Sector Erase algorithm. Sector erase modes allow
sectors of the array to be erased in one erase cycle. The
Automatic Sector Erase algorithm automatically programs
the specified sector(s) prior to electrical erase. The tim-
ing and verification of electrical erase are controlled in-
ternally within the device.
AUTOMATIC PROGRAMMING ALGORITHM
MXIC's Automatic Programming algorithm requires the
user to only write program set-up commands (including 2
unlock write cycle and A0H) and a program command
(program data and address). The device automatically
times the programming pulse width, provides the pro-
gram verification, and counts the number of sequences.
A status bit similar to Data# Polling and a status bit tog-
gling between consecutive read cycles, provide feedback
to the user as to the status of the programming opera-
tion.
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