ST = GND, Vdd_2.8, Vdd_3.0, Vdd_3.3, Vdd_XX, Vdd_YY.
Output is weakly pulled down
ST = GND, Vdd_2.5, Output is weakly pulled down
ST = GND, Vdd_1.8, Output is weakly pulled down
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10 March 2021
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SiT8008B
Low Power Programmable Oscillator
Table 1. Electrical Characteristics
(continued)
Parameters
Duty Cycle
Rise/Fall Time
Symbol
DC
Tr, Tf
Min.
45
–
–
–
–
Output High Voltage
VOH
90%
Typ.
–
1
1.3
–
–
–
Max.
55
2
2.5
2
2.7
–
Unit
%
ns
ns
ns
ns
Vdd
Condition
All Vdds. See Duty Cycle definition in
Figure 3
and
Footnote 6
20% - 80% Vdd_2.5, Vdd_2.8, Vdd_3.0, Vdd_3.3
20% - 80% Vdd_1.8
20% - 80% Vdd_XX
20% - 80% Vdd_YY
IOH = -4 mA (Vdd_3.0 and Vdd_3.3)
IOH = -3 mA (Vdd_2.8 and Vdd_ 2.5)
IOH = -2 mA (Vdd _1.8)
IOH = -4 mA (Vdd_3.0 and Vdd_3.3)
IOH = -3 mA (Vdd_2.8 and Vdd_ 2.5)
IOH = -2 mA (Vdd _1.8)
Pin 1, OE or ST
Pin 1, OE or ST
Pin 1, OE logic high or logic low, or ST logic high
Pin 1, ST logic low
Measured from the time Vdd reaches its rated minimum value
f = 110 MHz. For other frequencies, T_oe = 100 ns + 3 * cycles
Measured from the time ST pin crosses 50% threshold
f = 75 MHz, Vdd_1.8, Vdd_2.5, Vdd_2.8, Vdd_3.0, Vdd_3.3,
Vdd_XX,
f = 75 MHz, Vdd_YY
f = 75 MHz, Vdd_2.5, Vdd_2.8, Vdd_3.0, Vdd_3.3, Vdd_XX, Vdd_YY
f = 75 MHz, Vdd_1.8
f = 75 MHz, Integration bandwidth = 900 kHz to 7.5 MHz. Vdd_1.8,
Vdd_2.5, Vdd_2.8, Vdd_3.0, Vdd_3.3, Vdd_XX
f = 75 MHz, Integration bandwidth = 12 kHz to 20 MHz. Vdd_1.8,
Vdd_2.5, Vdd_2.8, Vdd_3.0, Vdd_3.3, Vdd_XX
f = 75 MHz, Integration bandwidth = 900 kHz to 7.5 MHz. Vdd_YY
f = 75 MHz, Integration bandwidth = 12 kHz to 20 MHz. Vdd_YY
LVCMOS Output Characteristics
Output Low Voltage
VOL
–
–
10%
Vdd
Input Characteristics
Input High Voltage
Input Low Voltage
Input Pull-up Impedance
VIH
VIL
Z_in
70%
–
50
2
Startup Time
Enable/Disable Time
Resume Time
RMS Period Jitter
T_start
T_oe
T_resume
T_jitt
–
–
–
–
–
Peak-to-peak Period Jitter
RMS Phase Jitter (random)
T_pk
T_phj
–
–
–
–
–
–
–
–
87
–
–
–
–
1.8
–
12
14
0.5
1.3
–
–
–
30%
150
–
5
130
5
Jitter
3
3.3
25
30
0.9
2
1.4
2.3
ps
ps
ps
ps
ps
ps
ps
ps
Vdd
Vdd
k
M
ms
ns
ms
Startup and Resume Timing
Table 2. Pin Description
Pin
Symbol
Output Enable
1
OE/ST/NC
̅ ̅̅
Functionality
H
[1]
: specified frequency output
L: output is high impedance. Only output driver is disabled.
H
[1]
: specified frequency output
L: output is low (weak pull down). Device goes to sleep mode.
Supply current reduces to I_std.
Any voltage between 0 and Vdd or Open
[1]
: Specified frequency
output. Pin 1 has no function.
Electrical ground
Oscillator output
Power supply voltage
[2]
Top View
OE/ST/NC
̅ ̅̅
Standby
No Connect
2
3
4
GND
OUT
VDD
Power
Output
Power
Figure 1. Pin Assignments
Notes:
1. In OE or ST mode, a pull-up resistor of 10 kΩ or less is recommended if pin 1 is not externally driven. If pin 1 needs to be left floating, use the NC option.
̅ ̅̅
2. A capacitor of value 0.1 µF or higher between Vdd and GND is required.
1.07
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SiT8008B
Low Power Programmable Oscillator
Table 3. Absolute Maximum Limits
Attempted operation outside the absolute maximum ratings may cause permanent damage to the part. Actual performance
of the IC is only guaranteed within the operational specifications, not at absolute maximum ratings.
Parameter
Storage Temperature
Vdd
Electrostatic Discharge
Soldering Temperature (follow standard Pb free soldering guidelines)
Junction Temperature
[3]
Note:
3. Exceeding this temperature for extended period of time may damage the device.
Min.
-65
-0.5
–
–
–
Max.
150
4
2000
260
150
Unit
°C
V
V
°C
°C
Table 4. Thermal Consideration
[4]
Package
7050
5032
3225
2520
2016
Note:
4. Refer to JESD51 for
JA
and
JC
definitions, and reference layout used to determine the
JA
and
JC
values in the above table.
JA, 4 Layer Board
(°C/W)
142
97
109
117
152
JA, 2 Layer Board
(°C/W)
273
199
212
222
252
JC, Bottom
(°C/W)
30
24
27
26
36
Table 5. Maximum Operating Junction Temperature
[5]
Max Operating Temperature (ambient)
70°C
85°C
Maximum Operating Junction Temperature
80°C
95°C
Note:
5. Datasheet specifications are not guaranteed if junction temperature exceeds the maximum operating junction temperature.
Table 6. Environmental Compliance
Parameter
Mechanical Shock
Mechanical Vibration
Temperature Cycle
Solderability
Moisture Sensitivity Level
Condition/Test Method
MIL-STD-883F, Method 2002
MIL-STD-883F, Method 2007
JESD22, Method A104
MIL-STD-883F, Method 2003
MSL1 @ 260°C
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Page 3 of 18
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SiT8008B
Low Power Programmable Oscillator
Test Circuit and Waveform
[6]
Vdd
Vout
Test Point
tr
4
Power
Supply
0.1 uF
1
2
3
15pF
(including probe
and fixture
capacitance)
tf
80% Vdd
50%
20% Vdd
High Pulse
(TH)
Period
Low Pulse
(TL)
Vdd
OE/ST Function
1 kΩ
Figure 1. Test Circuit
Note:
6. Duty Cycle is computed as Duty Cycle = TH/Period.
Figure 2. Waveform
Timing Diagrams
90% Vdd
Vdd
Vdd
50% Vdd
[7]
Pin 4 Voltage
T_start
No Glitch
during start up
ST Voltage
T_resume
CLK Output
HZ
T_start: Time to start from power-off
CLK Output
HZ
T_resume: Time to resume from ST
Figure 3. Startup Timing (OE/ ST̅ Mode)
̅ ̅
Figure 4. Standby Resume Timing ( ST̅ Mode Only)
̅ ̅
Vdd
50% Vdd
OE Voltage
T_oe
Vdd
OE Voltage
50% Vdd
T_oe
CLK Output
HZ
T_oe: Time to re-enable the clock output
CLK Output
HZ
T_oe: Time to put the output in High Z mode
Figure 5. OE Enable Timing (OE Mode Only)
Note:
7. SiT8008 has “no runt” pulses and “no glitch” output during startup or resume.
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