DDR4 SDRAM UDIMM
DDR4 SDRAM UDIMM
Based on 8Gb D-die
HMA851U6DJR6N
HMA81GU6DJR8N
HMA81GU7DJR8N
HMA82GU6DJR8N
HMA82GU7DJR8N
*SK hynix reserves the right to change products or specifications without notice.
Rev. 1.3 / Jan.2020
1
Revision History
Revision No.
0.1
1.0
1.1
1.2
1.3
History
Initial Release
Define IDD/IPP Specification
Add ECC UDIMM Specification
Add Diagram and Correct Typo
Define IDD/IPP Specification for 3200Mbps
Define IDD/IPP Specification for EDD UDIMM
Draft Date
Sep.2018
Jan.2019
Feb.2019
Jun.2019
Jan.2020
Remark
Rev. 1.3 / Jan.2020
2
Description
SK hynix Unbuffered DDR4 SDRAM DIMMs (Unbuffered Double Data Rate Synchronous DRAM Dual In-Line
Memory Modules) are low power, high-speed operation memory modules that use DDR4 SDRAM devices.
These Unbuffered SDRAM DIMMs are intended for use as main memory when installed in systems such as
PCs and workstations.
Features
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Power Supply: VDD=1.2V (1.14V to 1.26V)
VDDQ = 1.2V (1.14V to 1.26V)
VPP - 2.5V (2.375V to 2.75V)
VDDSPD=2.25V to 3.6V
Functionality and operations comply with the DDR4 SDRAM datasheet
16 internal banks
Bank Grouping is applied, and CAS to CAS latency (tCCD_L, tCCD_S) for the banks in the same or dif-
ferent bank group accesses are available
Data transfer rates: PC4-3200, PC4-2933, PC4-2666, PC4-2400, PC4-2133, PC4-1866, PC4-1600
Bi-Directional Differential Data Strobe
8 bit pre-fetch
Burst Length (BL) switch on-the-fly BL8 or BC4(Burst Chop)
Supports ECC error correction and detection
On-Die Termination (ODT)
Temperature sensor with integrated SPD for ECC UDIMM
This product is in compliance with the RoHS directive.
Per DRAM Addressability is supported
Internal Vref DQ level generation is available
Ordering Information
Part Number
HMA851U6DJR6N-VK/WM/XN
HMA81GU6DJR8N-VK/WM/XN
HMA81GU7DJR8N-VK/WM/XN
HMA82GU6DJR8N-VK/WM/XN
HMA82GU7DJR8N-VK/WM/XN
Density
4GB
8GB
8GB
16GB
16GB
Organization
512Mx64
1Gx64
1Gx72
2Gx64
2Gx72
Component Composition
512Mx16(H5AN8G6NDJR)*4
1Gx8(H5AN8G8NDJR)*8
1Gx8(H5AN8G8NDJR)*9
1Gx8(H5AN8G8NDJR)*16
1Gx8(H5AN8G8NDJR)*18
# of
ranks
1
1
1
2
2
Rev. 1.3 / Jan.2020
3
Key Parameters
MT/s
Grade
tCK
(ns)
1.25
1.071
0.937
0.833
0.75
0.682
0.625
CAS
Latency
(tCK)
11
13
15
17
19
21
22
tRCD
(ns)
13.75
(13.50)*
13.92
(13.50)*
14.06
(13.50)*
14.16
(13.75)*
14.25
(13.75)*
14.32
(13.75)*
13.75
tRP
(ns)
13.75
(13.50)*
13.92
(13.50)*
14.06
(13.50)*
14.16
(13.75)*
14.25
(13.75)*
14.32
(13.75)*
13.75
tRAS
(ns)
35
34
33
32
32
32
32
tRC
(ns)
48.75
(48.50)*
47.92
(47.50)*
47.06
(46.50)*
46.16
(45.75)*
46.25
(45.75)*
46.32
(45.75)*
47.0
CL-tRCD-tRP
DDR4-1600
DDR4-1866
DDR4-2133
DDR4-2400
DDR4-2666
DDR4-2933
DDR4-3200
-PB
-RD
-TF
-UH
-VK
-WM
-XN
11-11-11
13-13-13
15-15-15
17-17-17
19-19-19
21-21-21
22-22-22
*SK hynix DRAM devices support optional downbinning to CL22, CL21, CL19, CL17, CL15, CL13 and CL11. SPD setting is pro-
grammed to match.
Address Table
4GB(1Rx16)
# of Bank Groups
Bank Address BG Address
Bank Address in a BG
Row Address
Column Address
Page size
2
BG0
BA0~BA1
A0~A15
A0~ A9
2KB
8GB(1Rx8)
4
BG0~BG1
BA0~BA1
A0~A15
A0~ A9
1 KB
16GB(2Rx8)
4
BG0~BG1
BA0~BA1
A0~A15
A0~ A9
1 KB
Rev. 1.3 / Jan.2020
4
Pin Descriptions
Pin Name
A0-A17
1
BA0, BA1
BG0, BG1
RAS_n
2
CAS_n
3
WE_n
4
CS0_n, CS1_n,
CKE0, CKE1
ODT0, ODT1
ACT_n
DQ0-DQ63
CB0-CB7
Description
SDRAM address bus
SDRAM bank select
SDRAM bank group select
SDRAM row address strobe
SDRAM column address strobe
SDRAM write enable
DIMM Rank Select Lines
SDRAM clock enable lines input
SDRAM on-die termination control
lines input
SDRAM activate
DIMM memory data bus
DIMM ECC check bits
Pin Name
SCL
SDA
SA0-SA2
PARITY
VDD
C0, C1, C2
12V
VREFCA
VSS
VDDSPD
ALERT_n
VPP
Description
I
2
C serial bus clock for SPD-TSE
I
2
C serial bus line for SPD-TSE
I
2
C slave address select for SPD-TSE
SDRAM parity input
SDRAM I/OO and core power supply
Chip ID lines
Optional power Supply on socket but
not used on UDIMM
SDRAM command/address reference
supply
Power supply return (ground)
Serial SPD-TSE positive power supply
SDRAM ALERT_n output
SDRAM Supply
Dummy loads for mixed populations
TDQS0_t-TDQS8_t
of x4 based and x8 based RDIMMs.
TDQS0_c-TDQS8_c
Not used on UDIMMs.
DQS0_t-DQS8_t
DQS0_c-DQS8_c
DM0_n-DM8_n,
DBI0_n-DBI8_n
CK0_t, CK1_t
CK0_c, CK1_c
SDRAM data strobes
(positive line of differential pair)
SDRAM data strobes
(negative line of differential pair)
SDRAM data masks/data bus inersion
(x8-based x72 DIMMs)
SDRAM clock (positive line of differen-
tial pair)
SDRAM clock (positive line of differen-
tial pair)
RESET_n
EVENT_n
VTT
RFU
Set DRAMs to a Known State
SPD signals a thermal event has
occurred
SDRAM I/O termination supply
Reserved for future use
1. Address A17 is not valid for x8 and x16 based SDRAMs. For UDIMMs, this connection pin is NC.
2. RAS_n is a multiplexed function with A16.
3. CAS_n is a multiplexed function with A15.
4. WE_n is a multiplexed function with A14.
Rev. 1.3 / Jan.2020
5
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