sample frequency (4 x 44.1kHz; 4 times oversampling). (5) Offset error at bipolar zero. (6) Measured using an OPA27 and 10kΩ feedback and an A-weighted filter.
(7) Bipolar Zero.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
Input Logic Voltage ................................................................. –1V to +V
CC
Storage Temperature ...................................................... –60°C to +100°C
Lead Temperature (soldering, 10s) ................................................ +300°C
PACKAGE INFORMATION
(1)
MODEL
PCM58P
PCM58P, J
PCM58P, K
PACKAGE
28-Pin Plastic DIP
28-Pin Plastic DIP
28-Pin Plastic DIP
PACKAGE DRAWING
NUMBER
215
215
215
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix D of Burr-Brown IC Data Book.
Use 400Hz High-Pass
Filter and 30kHz
Low-Pass Filter
Meter Settings
Distortion
Analyzer
Programmable
Gain Amp
0dB to 60dB
Low-Pass
Filter
(Toko APQ-25
or Equivalent)
LOW-PASS FILTER
CHARACTERISTIC
0
–20
(Shiba Soku Model
725 or Equivalent)
Gain (dB)
Parallel-to-Serial
Conversion
DUT
(PCM58P)
Clock
Latch Enable
Sampling Rate = 44.1kHz X 4 (176.4kHz)
Output Frequency = 991Hz
–40
–60
–80
–100
Binary
Counter
Digital Code
(EPROM)
–120
1 10
1
10
2
10
3
10
4
10
5
Frequency (Hz)
Timing
Logic
FIGURE 1. PCM58P Production THD+N Test Setup.
DISCUSSION OF
SPECIFICATIONS
TOTAL HARMONIC DISTORTION + NOISE
The key specification for the PCM58P is total harmonic
distortion plus noise. Digital data words are read into the
PCM58P at four times the standard audio sampling frequency
of 44.1kHz or 176.4kHz such that a sinewave output of 991Hz
is realized. For production testing, the output of the DAC
goes to a programmable gain amplifier to provide gain at
lower signal output test levels and then through a 20kHz
low pass filter before being fed into an analog type distortion
analyzer. Figure 1 shows a block diagram of the production
THD+N test setup.
®
3
PCM58P
In terms of signal measurement, THD+N is the ratio of
Distortion
RMS
+ Noise
RMS
/ Signal
RMS
expressed in dB. For
the PCM58P, THD+N is 100% tested at three different output
levels using the test setup shown in Figure 1. It is significant
to note that this test setup does not include any output
deglitching circuitry. This means the PCM58P even meets
its –60dB THD+N specification without use of external
deglitchers.
ABSOLUTE LINEARITY
Even though absolute integral and differential linearity specs
are not given for the PCM58P, the extremely low THD+N
performance is typically indicative of 15-bit to 16-bit integral
linearity in the DAC depending on the grade specified. The
relationship between THD+N and linearity, however, is not
such that an absolute linearity specification for every indi-
vidual output code can be guaranteed.
IDLE CHANNEL SNR
Another appropriate spec for a digital audio converter is idle
channel signal-to-noise ratio (idle channel SNR). This is the
ratio of the noise on the DAC output at bipolar zero in relation
to the full scale range of the DAC. The output of the DAC
is band-limited from 20Hz to 20kHz and an A-weighted filter
is applied to make this measurement. The idle channel SNR
for the PCM58P is typically greater than +126dB, making
it ideal for low-noise applications.
OFFSET, GAIN, AND TEMPERATURE DRIFT
Although the PCM58P is primarily meant for use in dynamic
applications, specifications are also given for more traditional
DC parameters such as gain error, bipolar zero offset error,
and temperature gain drift and offset drift.
TIMING CONSIDERATIONS
The PCM58P accepts TTL-compatible logic input levels.
Noise immunity is enhanced by the use of Schmitt trigger
input architectures on all input signal lines. The data format
of the PCM58P is binary two’s complement (BTC) with the
most significant bit (MSB) being first in the serial input bit
stream. Table I describes the exact input data to voltage output
coding relationship. Any number of bits can precede the 18
bits to be loaded as only the last 18 will be transferred to
the parallel DAC register after LE (P17; latch enable) has
gone low.
The individual DAC serial input data bit shifts transfer are
triggered on positive CLK edges. The serial to parallel data
transfer to the DAC occurs on the falling edge of LE (P17).
Refer to Figure 2 for graphical relationships of these signals.
MAXIMUM CLOCK RATE
The maximum clock rate of 16.9mHz for the PCM58P is
derived by multiplying the standard audio sample rate of
44.1kHz times sixteen (16X oversampling) times the standard
audio word bit length of 24 (44.1kHz x 16 x 24 = 16.9mHz).
Note that this clock rate accommodates a 24-bit word length,
even though only 18 bits are actually being used.
DIGITAL INPUT
Binary Two’s
Complement (BTC)
3FFFF Hex
20000 Hex
1FFFF Hex
00000 Hex
ANALOG OUTPUT
Voltage (V)
V
OUT
Mode
+2.9999943
0.0000000
–0.0000057
–3.0000000
Current (mA)
I
OUT
Mode
–0.9999981
0.0000000
+0.0000019
+1.0000000
DAC Output
+FS
BPZ
BPZ – 1LSB
–FS
TABLE I. PCM60P Input/Output Relationships.
P16 (Clock)
P18 (Data)
1
MSB
2
3
4
10
11
12
13
14
15
16
17
18
LSB
1
P17 (Latch Enable)
NOTES: (1) If clock is stopped between input of 18-bit data words, latch enable (LE) must remain low until after the first clock of the next 18-bit data word stream.
(2) Data format is binary two’s complement (BTC). Individual data bits are clocked in on the corresponding positive clock edge. (3) Latch enable (LE) must
remain low at least one clock cycle after going negative. (4) Latch enable (LE) must be high for at least one clock cycle before going negative.
FIGURE 2. PCM58P Timing Diagram.
®
PCM58P
4
“STOPPED-CLOCK” OPERATION
The PCM58P is normally operated with a continuous clock
input signal. If the clock is to be stopped in between input
data words, the last 18-bits shifted in are not actually shifted
from the serial register to the latched parallel DAC register
until LE (latch enable) goes low. If the clock input (P16,
CLK) is stopped between data words, LE (P17) must remain
low until after the first clock cycle of the next data word
to insure proper DAC operation. In either case, the setup and
hold times for DATA and LE must still be observed as shown
in Figure 3.
>40ns
Data
Input
LSB
MSB
>15ns >15ns
Clock
Input
>40ns
>100ns
>15ns
Latch
Enable
>One Clock Cycle
>One Clock Cycle
>40ns
>5ns
INSTALLATION
Refer to Figure 4 for proper connection of the PCM58P in
the voltage-out mode using the internal feedback resistor.
The feedback resistor connections (P7 and P10) should be
connected to ACOM (P8) if not used. The PCM58P requires
only a +5V and –12V supply. It is very important that these
supplies be as “clean” as possible to reduce coupling of supply
noise to the output. Power supply decoupling capacitors
shown in Figure 4 should be used, regardless of how good
the supplies are to maximize power supply rejection. All
grounds should be connected to the analog ground plane as
close to the PCM58P as possible.
FIGURE 3. PCM58P Setup and Hold Timing Diagram.
FILTER CAPACITOR REQUIREMENTS
As shown in Figure 4, other various decoupling capacitors
are required around the supply and reference points with no
special tolerances being required. Placement of all capacitors
should be as close to the appropriate pins of the PCM58P
as possible to reduce noise pickup from surrounding circuitry.
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