BSI
FEATURES
Ultra Low Power/Voltage CMOS SRAM
32K X 8 bit
DESCRIPTION
BS62UV256
• Ultra low operation voltage : 1.8V ~ 3.6V
• Ultra low power consumption :
Vcc = 2.0V C-grade : 10mA (Max.) operating current
I- grade : 15mA (Max.) operating current
0.005uA (Typ.) CMOS standby current
Vcc = 3.0V C-grade : 20mA (Max.) operating current
I-grade : 25mA (Max.) operating current
0.01uA (Typ.) CMOS standby current
• High speed access time :
-15
150ns (Max.) at Vcc = 2.0V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE and OE options
The BS62UV256 is a high performance, ultra low power CMOS
Static Random Access Memory organized as 32,768 words by 8 bits
and operates from a wide range of 1.8V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.005uA and maximum access time of 150ns in 2V operation.
Easy memory expansion is provided by an active LOW chip
enable (CE), and active LOW output enable (OE) and three-state
output drivers.
The BS62UV256 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS62UV256 is available in the JEDEC standard 28 pin
330mil Plastic SOP, 8mmx13.4mm TSOP (normal type), 300mil Plastic
SOJ and 600mil Plastic DIP.
PRODUCT FAMILY
PRODUCT
FAMILY
BS62UV256SC
BS62UV256TC
BS62UV256PC
BS62UV256JC
BS62UV256DC
BS62UV256SI
BS62UV256TI
BS62UV256PI
BS62UV256JI
BS62UV256DI
OPERATING
TEMPERATURE
Vcc
RANGE
SPEED
(ns)
Vcc=
2.0V
POWER DISSIPATION
STANDBY
Operating
(I
CCSB1
, Max)
Vcc=
Vcc=
3.0V
2.0V
(I
CC
, Max)
Vcc=
Vcc=
3.0V
2.0V
PKG
TYPE
SOP-28
TSOP-28
PDIP-28
SOJ-28
DICE
SOP-28
TSOP-28
PDIP-28
SOJ-28
DICE
+0 C to +70 C
O
O
1.8V ~ 3.6V
150
0.2uA
0.1uA
20mA
10mA
-40 C to +85 C
O
O
1.8V ~ 3.6V
150
0.4uA
0.3uA
25mA
15mA
PIN CONFIGURATIONS
BLOCK DIAGRAM
28
27
26
25
24
23
VCC
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
8
Data
Input
Buffer
8
A5
A6
A7
A12
A14
A13
A8
A9
A11
512
Column I/O
Write Driver
Sense Amp
64
Column Decoder
12
CE
WE
OE
Vdd
Gnd
A4 A3 A2 A1 A0 A10
Control
Address Input Buffer
Buffer
Address
Input
•
1
2
3
4
5
6
11
12
13
14
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
18
Row
Decoder
512
Memory Array
512 x 512
7
BS62UV256SC
22
8
BS62UV256SI
21
BS62UV256PC
9
BS62UV256PI
20
19
10
18
17
16
15
OE
A11
A9
A8
A13
WE
VCC
A14
A12
A7
A6
A5
A4
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
BS62UV256TC
BS62UV256TI
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
A1
A2
8
Data
Output
Buffer
8
Brilliance Semiconductor Inc
.
reserves the right to modify document contents without notice.
R0201-BS62UV256
•
1
Revision 2.2
April 2001
BSI
PIN DESCRIPTIONS
BS62UV256
Function
These 15 address inputs select one of the 32768 x 8-bit words in the RAM
CE is active LOW. Chip enables must be active to read from or write to the device. If
chip enable is not active, the device is deselected and is in a standby power mode.
The DQ pins will be in the high impedance state when the device is deselected.
Name
A0-A14 Address Input
CE Chip Enable Input
WE Write Enable Input
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
DQ0-DQ7 Data Input/Output
Ports
Vcc
Gnd
These 8 bi-directional ports are used to read data from or write data into the RAM.
Power Supply
Ground
TRUTH TABLE
MODE
Not selected
Output Disabled
Read
Write
WE
X
H
H
L
CE
H
L
L
L
OE
X
H
L
X
I/O OPERATION
High Z
High Z
D
OUT
D
IN
Vcc CURRENT
I
CCSB
, I
CCSB1
I
CC
I
CC
I
CC
ABSOLUTE MAXIMUM RATINGS
(1)
SYMBOL
V
TERM
T
BIAS
T
STG
P
T
I
OUT
PARAMETER
Terminal Voltage with
Respect to GND
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
OPERATING RANGE
UNITS
V
O
RATING
-0.5 to
Vcc+0.5
-40 to +125
-60 to +150
1.0
20
RANGE
Commercial
Industrial
AMBIENT
TEMPERATURE
0
O
C to +70
O
C
-40
O
C to +85
O
C
Vcc
1.8V ~ 3.6V
1.8V ~ 3.6V
C
C
O
W
mA
CAPACITANCE
(1)
(TA = 25
o
C, f = 1.0 MHz)
SYMBOL
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
C
IN
C
DQ
PARAMETER
Input
Capacitance
Input/Output
Capacitance
CONDITIONS
MAX.
UNIT
V
IN
=0V
V
I/O
=0V
6
8
pF
pF
1. This parameter is guaranteed and not tested.
R0201-BS62UV256
2
Revision 2.2
April 2001
BSI
DC ELECTRICAL CHARACTERISTICS
( TA = 0
o
C to + 70
o
C )
PARAMETER
NAME
V
IL
V
IH
I
IL
I
OL
V
OL
V
OH
I
CC
I
CCSB
I
CCSB1
BS62UV256
TEST CONDITIONS
Vcc=2.0V
Vcc=3.0V
Vcc=2.0V
Vcc=3.0V
PARAMETER
Guaranteed Input Low
Voltage
(2)
Guaranteed Input High
Voltage
(2)
Input Leakage Current
Output Leakage Current
Output Low Voltage
Output High Voltage
Operating Power Supply
Current
Standby Current-TTL
Standby Current-CMOS
MIN. TYP.
(1)
MAX.
-0.5
1.4
2.0
--
--
Vcc=2.0V
Vcc=3.0V
Vcc=2.0V
Vcc=3.0V
Vcc=2.0V
UNITS
V
V
uA
uA
V
V
mA
mA
uA
--
--
--
--
--
--
--
--
--
--
0.005
0.01
0.6
0.8
Vcc+0.2
1
1
0.4
--
10
20
0.5
1.0
0.1
0.2
Vcc = Max, V
IN
= 0V to Vcc
Vcc = Max, CE = V
IH
, or OE = V
IH
,
V
I/O
= 0V to Vcc
Vcc = Max, I
OL
= 1mA
Vcc = Min, I
OH
= -0.5mA
CE = V
IL
, I
DQ
= 0mA, F = Fmax
(3)
CE = V
IH
, I
DQ
= 0mA
CE
V
IN
Vcc-0.2V,
Vcc - 0.2V or V
IN
--
1.6
2.4
--
--
--
--
--
--
Vcc=3.0V
Vcc=2.0V
Vcc=3.0V
Vcc=2.0V
0.2V
Vcc=3.0V
1. Typical characteristics are at TA = 25
o
C.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/t
RC
.
DATA RETENTION CHARACTERISTICS
( TA = 0
o
C to + 70
o
C )
SYMBOL
V
DR
I
CCDR
t
CDR
t
R
PARAMETER
Vcc for Data Retention
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
CE
V
IN
CE
V
IN
TEST CONDITIONS
Vcc - 0.2V
Vcc - 0.2V or V
IN
Vcc -0.2V
Vcc - 0.2V or V
IN
0.2V
0.2V
MIN.
1.5
--
0
T
RC (2)
TYP.
(1)
--
0.005
--
--
MAX.
--
0.1
--
--
UNITS
V
uA
ns
ns
See Retention Waveform
1. Vcc = 1.5V, T
A
= + 25
O
C
2. t
RC
= Read Cycle Time
LOW V
CC
DATA RETENTION WAVEFORM (1)
( CE Controlled )
Data Retention Mode
Vcc
V
IH
Vcc
V
DR
≥
1.5V
Vcc
t
CDR
CE
≥
Vcc - 0.2V
t
R
V
IH
CE
R0201-BS62UV256
3
Revision 2.2
April 2001
BSI
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level
Vcc/0V
5ns
0.5Vcc
WAVEFORM
INPUTS
MUST BE
STEADY
BS62UV256
KEY TO SWITCHING WAVEFORMS
OUTPUTS
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
WILL BE
CHANGE
FROM L TO H
CHANGE :
STATE
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
AC TEST LOADS AND WAVEFORMS
2V
OUTPUT
100PF
INCLUDING
JIG AND
SCOPE
MAY CHANGE
FROM H TO L
1333
Ω
1333
Ω
2V
OUTPUT
MAY CHANGE
FROM L TO H
DON T CARE:
ANY CHANGE
PERMITTED
DOES NOT
APPLY
,
5PF
2000
Ω
INCLUDING
JIG AND
SCOPE
2000
Ω
FIGURE 1A
THEVENIN EQUIVALENT
800
Ω
FIGURE 1B
OUTPUT
1.2V
ALL INPUT PULSES
Vcc
GND
10%
90% 90%
10%
→
←
→
←
5ns
FIGURE 2
AC ELECTRICAL CHARACTERISTICS
( TA = 0
o
C to + 70
o
C, Vcc = 2.0V )
READ CYCLE
JEDEC
PARAMETER
NAME
PARAMETER
NAME
DESCRIPTION
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Output Disable to Output in High Z
Output Disable to Output Address Change
BS62UV256 -15
MIN. TYP. MAX.
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
AVAX
t
AVQV
t
ELQV
t
GLQV
t
ELQX
t
GLQX
t
EHQZ
t
GHQZ
t
AXOX
t
RC
t
AA
t
ACS
t
OE
t
CLZ
t
OLZ
t
CHZ
t
OHZ
t
OH
150
--
--
--
10
10
0
0
10
--
--
--
--
--
--
--
--
--
--
150
150
100
--
--
35
30
--
R0201-BS62UV256
4
Revision 2.2
April 2001
BSI
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1
(1,2,4)
BS62UV256
t
RC
ADDRESS
t
D
OUT
t
OH
AA
t
OH
READ CYCLE2
(1,3,4)
CE
t
t
D
OUT
(5)
CLZ
ACS
t
CHZ
(5)
READ CYCLE3
(1,4)
t
RC
ADDRESS
t
OE
AA
t
OE
CE
t
OH
t
OLZ
t
ACS
t
CLZ
(5)
t
OHZ
(5)
(1,5)
t
CHZ
D
OUT
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE = V
IL
.
3. Address valid prior to or coincident with CE transition low.
4. OE = V
IL
.
5. Transition is measured
±
500mV from steady state with C
L
= 5pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
R0201-BS62UV256
5
Revision 2.2
April 2001
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