EEWORLDEEWORLDEEWORLD

Part Number

Search

3640A25026N7FCB

Description
Ceramic Capacitor, Multilayer, Ceramic, 250V, 1% +Tol, 1% -Tol, C0G, -/+30ppm/Cel TC, 0.0267uF, 3640,
CategoryPassive components    capacitor   
File Size151KB,4 Pages
ManufacturerKnowles
Websitehttp://www.knowles.com
Download Datasheet Parametric View All

3640A25026N7FCB Overview

Ceramic Capacitor, Multilayer, Ceramic, 250V, 1% +Tol, 1% -Tol, C0G, -/+30ppm/Cel TC, 0.0267uF, 3640,

3640A25026N7FCB Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
Objectid882257373
package instruction, 3640
Reach Compliance Codecompliant
ECCN codeEAR99
capacitance0.0267 µF
Capacitor typeCERAMIC CAPACITOR
dielectric materialsCERAMIC
high2.5 mm
JESD-609 codee0
length9.2 mm
multi-layerYes
negative tolerance1%
Number of terminals2
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Package formSMT
method of packingBulk
positive tolerance1%
Rated (DC) voltage (URdc)250 V
series3640(250,FGJK,C0G)
size code3640
Temperature characteristic codeC0G
Temperature Coefficient-/+30ppm/Cel ppm/°C
Terminal surfaceTin/Lead (Sn90Pb10) - with Nickel (Ni) barrier
width10.16 mm
Multilayer
Summary
Ceramic
Capacitors
Technical
Definitions of Ultra-Stable and Stable
Multilayer Ceramic Capacitors are generally divided into classes
which are defined by the capacitance temperature characteristics
over specified temperature ranges.
These are designated by alpha numeric codes.
Code definitions are summarised below and are also available in the
relevant national and international specifications.
1. C0G - Ultra Stable Class 1 Ceramic (EIA Class 1)
Spec.
CECC
EIA
MIL
Classification
1B/CG
C0G (NP0)
CG (BP)
Temperature
range °C
-55 +125
-55 +125
-55 +125
Maximum
capacitance change
0 ± 30ppm/°C
0 ± 30ppm/°C
0 ± 30ppm/°C
Syfer
dielectric code
C
C
C
Capacitors within this class have a dielectric constant range from 10
to 100. They are used in applications which require ultra stable
dielectric characteristics with negligible dependence of capacitance
and dissipation factor with time, voltage and frequency. They
exhibit the following characteristics:-
a) Time does not significantly affect capacitance and dissipation
factor (Tan
δ)
– no ageing.
b) Capacitance and dissipation factor are not affected by voltage.
c) Linear temperature coefficient.
2. X7R – Stable Class II Ceramic (EIA Class II)
Maximum capacitance change %
over temperature range
No DC volt applied
±20
±15
±15
±15
±15
±20
Rated DC Volt
+20 -30
+15 -25
-
+15 -25
+20 -30
Syfer
dielectric
code
R
X
B
X
B
R
Spec.
CECC
Classification
2C1
2R1
2X1
X7R
BX
BZ
Temperature
range °C
-55 +125
-55 +125
-55 +125
-55 +125
-55 +125
-55 +125
EIA
MIL
Capacitors of this type have a dielectric constant range of 1000-
4000, and also have a non-linear temperature characteristic which
exhibits a dielectric constant variation of less than ±15% (2R1)
from its room temperature value, over the specified temperature
range. Generally used for by-passing (decoupling), coupling,
filtering, frequency discrimination, DC blocking and voltage transient
suppression with greater volumetric efficiency than Class l units,
whilst maintaining stability within defined limits.
Capacitance and dissipation factor are affected by:-
Time
(Ageing)
Voltage
(AC or DC)
Frequency
4
Waiting online
Draw a diagram to illustrate the allocated storage space and initialized value of the following statement: byte_var db 3 dup(-1,?,3(dup(4)), thank you, waiting online...
sjh008 Embedded System
Problem with TransBusAddrToStatic() under CE6.0
I'm working on sharing IRQ under CE recently, and I've seen some examples that call TransBusAddrToStatic() function to convert address after LoadIntChainHandler(). I don't understand what the function...
eadge Embedded System
Analysis of the working principles of seven triode collector DC circuits 2
[b]2. Typical collector DC circuit of NPN transistor with positive power supply (part 2) [/b] [align=left] [color=rgb(34, 34, 34)] [font="] The figure below shows the typical collector DC circuit of N...
tiankai001 Analog electronics
Can you help me figure out why this frequency divider program is wrong?
--Divide the 1khz standard signal std_clk into CE outputs with a period of 2 seconds and a duty cycle of 50% LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY freq_division_1 ISPORT(std_clk,reset:IN S...
eeleader-mcu FPGA/CPLD
Plasma speakers
[size=14px]How many of you have played with plasma speakers? I wonder if many are interested. I am very interested. I have been following the development of this technology since I found it in 2010. I...
shipeng Talking
What kind of FPGA development board do beginners need?
What kind of FPGA development board do beginners need?...
fpgaw FPGA/CPLD

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 1830  2523  1329  842  324  37  51  27  17  7 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号