PRELIMINARY
FEBRUARY 2007
XRK32308
3.3V ZERO DELAY BUFFER
REV. P1.0.3
GENERAL DESCRIPTION
FUNCTIONAL DESCRIPTION
XRK32308 is a 3.3V Zero Delay Buffer designed to
distribute high-speed clocks in PC, workstation,
datacom, telecom, and other high-performance
applications.
The part has an on-chip PLL which locks to an input
clock presented on the REF pin. The PLL feedback is
required to be driven into the FB pin, and can be
obtained from one of the outputs. The input-to-output
skew is guaranteed to be less than 350 ps, and
output-to-output skew is guaranteed to be less than
200 ps.
XRK32308 has two banks of four outputs each.
These can be controlled by the Select inputs as
shown in Table 2, “Select Input Decoding,” on page 2.
If all output clocks are not required, Bank B can be
three-stated. The select inputs also allow the input
clock to be directly applied to the output for chip and
system testing purposes.
Multiple XRK32308 devices can accept the same
input clock and distribute it in a system. In this case,
the skew between the outputs of two devices is
guaranteed to be less than 700 ps.
XRK32308 devices are available in five different
configurations, as shown in Table 3, “Available
XRK32308 Configurations,” on page 3.
The XRK32308–1 is the base part, where the output
frequencies equal the reference if there is no counter
in the feedback path.
The XRK32308–1H is the high-drive version of the –
1. Rise and fall times on this device are faster.
The XRK32308–2 allows the user to obtain 1X, and
2X or X/2 depending on which Bank sources the FB
signal.
The XRK32308–3 allows the user to obtain 4X and
2X frequencies or 1X and 2X.
The XRK32308–4 enables the user to obtain 2X
clocks on all outputs.
The XRK32308–5H is a high-drive version with REF/
2 on both banks.
FEATURES
•
Zero input-output propagation delay, adjustable by
capacitive load on FB input
•
Multiple configurations, see “Available XRK32308
Configurations” table
•
Multiple low-skew outputs
•
Two banks of four outputs, three-stateable by two
select inputs
•
10-MHz to 120-MHz operating range
•
75ps typical cycle-to-cycle jitter (15pF, 66MHz)
•
Space-saving 16-pin 150-mil SOIC package, 16-pin
TSSOP or 16-pin QFN
•
3.3V operation
•
Industrial and commercial temperature available
F
IGURE
1. B
LOCK
D
IAGRAM AND
P
IN
C
ONFIGURATION OF THE
XRK32308
/2
PLL
REF
/2
Extra Divider (-3, -4)
Extra Divider (-5H)
S2
S1
MUX
FB
QA0
QA1
QA2
QA3
QA0 REF
FB
QA3
REF
QA0
QA1
V
DD
GND
QB0
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
FB
QA3
QA2
V
DD
GND
QB3
QB2
S1
QA1
VDD
GND
QB0
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
QA2
VDD
GND
QB3
Select Input
Decoding
/2
QB0
QB1
Extra Divider (-2, -3)
QB2
QB3
QB1
S2
QB1
S2
S1
QB2
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
•
(510) 668-7000
•
FAX (510) 668-7017
•
www.exar.com
XRK32308
3.3V ZERO DELAY BUFFER
PRELIMINARY
REV. P1.0.3
T
ABLE
1: P
IN
D
ESCRIPTION
P
IN
S
IGNAL
SOIC/TSSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
QFN
15
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
REF
[1]
QA0
[2]
QA1
[2]
V
DD
GND
QB0
[2]
QB1
[2]
S2
[3]
S1
[3]
QB2
[2]
QB3
[2]
GND
V
DD
QA2
[2]
QA3
[2]
FB
Input reference frequency
Clock output, Bank A
Clock output, Bank A
3.3V supply
Ground
Clock output, Bank B
Clock output, Bank B
Select input, bit 2
Select input, bit 1
Clock output, Bank B
Clock output, Bank B
Ground
3.3V supply
Clock output, Bank A
Clock output, Bank A
PLL feedback input
D
ESCRIPTION
T
ABLE
2: S
ELECT
I
NPUT
D
ECODING
S2
0
0
1
1
N
OTES
:
1.
2.
3.
4.
Weak pull-down.
Weak pull-down on all outputs.
Weak pull-ups on these inputs.
Outputs inverted on XRK32308–2 and XRK32308–3 in bypass mode, S2 = 1 and S1 = 0.
S1
0
1
0
1
QA0-QA3
Three-State
Driven
Driven
[4]
Driven
QB0-QB3
Three-State
Three-State
Driven
[4]
Driven
O
UTPUT
S
OURCE
PLL
PLL
Reference
PLL
2
PRELIMINARY
REV. P1.0.3
XRK32308
3.3V ZERO DELAY BUFFER
T
ABLE
3: A
VAILABLE
XRK32308 C
ONFIGURATIONS
D
EVICE
XRK32308-1
XRK32308-1H
XRK32308-2
XRK32308-2
XRK32308-3
XRK32308-3
XRK32308-4
XRK32308-5H
N
OTES
:
5.
Output phase is indeterminant (0° or 180° from input clock). If phase integrity is required, use the XRK32308–2.
F
EEDBACK
F
ROM
Bank A or Bank B
Bank A or Bank B
Bank A
Bank B
Bank A
Bank B
Bank A or Bank B
Bank A or Bank B
B
ANK
A F
REQUENCY
Reference
Reference
Reference
2 X Reference
2 X Reference
4 X Reference
2 X Reference
Reference/2
B
ANK
B F
REQUENCY
Reference
Reference
Reference/2
Reference
Reference or Reference
[5]
2 X Reference
2 X Reference
Reference/2
ZERO DELAY AND SKEW CONTROL
F
IGURE
2. REF I
NPUT TO
QA
X
/QB
X
D
ELAY VS
D
IFFERENCE IN
L
OADING BETWEEN
FB
AND
QA
X
/QB
X
P
INS
1500
1000
REF Input to QAx/QBx Delay (ps)
500
0
-30
-25
-20
-15
-10
-5
0
5
10
15
20
25
30
-500
-1000
-1500
Output Load Difference: FB Load - QAx/QBx Load (pF)
Note: Target only, actual characterization curve may be slightly different.
To close the feedback loop of the XRK32308, the FB pin can be driven from any of the eight available output
pins. The output driving the FB pin will be driving a total load of 7 pF plus any additional load that it drives. The
relative loading of this output (with respect to the remaining outputs) can adjust the input-output delay. This is
shown in the graph above.
For applications requiring zero input-output delay, all outputs including the one providing feedback should be
equally loaded. If input-output delay adjustments are required, use the above graph to calculate loading
differences between the feedback output and remaining outputs.
For zero output-output skew, be sure to load outputs equally.
3
XRK32308
3.3V ZERO DELAY BUFFER
PRELIMINARY
REV. P1.0.3
T
ABLE
4: A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage to Ground Potential
DC Input Voltage (Except Ref)
DC Input Voltage REF
Storage Temperature
Junction Temperature
Static Discharge Voltage (per MIL-STD-883, Method 3015)
-0.5V to +7.0V
-0.5V to V
DD
+0.5V
-0.5 to 7V
-65°C to +150°C
150°C
>2000V
T
ABLE
5: O
PERATING
C
ONDITIONS FOR
XRK32308 C
OMMERCIAL
T
EMPERATURE
D
EVICES
P
ARAMETER
V
DD
T
A
C
L
Load Capacitance, from 100MHz to 120MHz
C
IN
t
PU
Input Capacitance
[6]
Power-up time for all V
DD
s to reach minimum
specified voltage (power ramps must be monotonic)
-
-
0.05
15
7
50
pF
pF
ms
Supply Voltage
Operating Temperature (Ambient Temperature)
Load Capacitance, below 100MHz
D
ESCRIPTION
M
IN
3.0
0
-
M
AX
3.6
70
30
U
NIT
V
°C
pF
N
OTES
:
6.
Applies to both Ref Clock and FB.
T
ABLE
6: E
LECTRICAL
C
HARACTERISTICS FOR
XRK32308 C
OMMERCIAL
T
EMPERATURE
D
EVICES
P
ARAMETER
V
IL
V
IH
I
IL
I
IH
V
OL
D
ESCRIPTION
Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
Output Low Voltage
[7]
V
IN
=0V
V
IN
=V
DD
I
OL
= 8mA (-1, -2, -3, -4)
I
OL
= 12mA (-1H, -5H)
V
OH
Output High Voltage
[7]
I
OH
= -8mA (-1, -2, -3, -4)
I
OH
= -12mA (-1H, -5H)
2.4
-
V
T
EST
C
ONDITIONS
M
IN
-
2.0
-
-
-
M
AX
0.8
-
50.0
100.0
0.4
U
NIT
V
V
µA
µA
V
4
PRELIMINARY
REV. P1.0.3
XRK32308
3.3V ZERO DELAY BUFFER
T
ABLE
6: E
LECTRICAL
C
HARACTERISTICS FOR
XRK32308 C
OMMERCIAL
T
EMPERATURE
D
EVICES
P
ARAMETER
D
ESCRIPTION
T
EST
C
ONDITIONS
Unloaded outputs, 100-MHz REF,
Select inputs at V
DD
or GND
M
IN
-
-
-
-
M
AX
45.0
70
(-1H, -5H)
32.0
18.0
U
NIT
mA
mA
mA
mA
I
DD
Supply Current
Unloaded outputs, 66-MHz REF
(-1, -2, -3, -4)
Unloaded outputs, 33-MHz REF
(-1, -2, -3, -4)
N
OTES
:
7.
Parameter is guaranteed by design and characterization. Not 100% tested in production.
T
ABLE
7: S
WITCHING
C
HARACTERISTICS FOR
XRK32308 C
OMMERCIAL
T
EMPERATURE
D
EVICES[8]
P
ARAMETER
N
AME
T
EST
C
ONDITIONS
30-pF load, All devices
t
1
Output Frequency
20-pF load, -1H, -5H devices
[9]
15-pF load, -1, -2, -3, -4 devices
Measured at 1.4V, F
OUT
=66.66MHz
30-pF load
Measured at 1.4V, F
OUT
<50.0MHz
15-pF load
Measured between 0.8V and 2.0V,
30-pF load
Measured between 0.8V and 2.0V,
15-pF load
Measured between 0.8V and 2.0V,
30-pF load
Measured between 0.8V and 2.0V,
30-pF load
Measured between 0.8V and 2.0V,
15-pF load
Measured between 0.8V and 2.0V,
30-pF load
M
IN
10
10
10
40.0
T
YP
-
-
-
50.0
M
AX
100
120
120
60.0
U
NIT
MHz
MHz
MHz
%
DC
Duty Cycle
[7]
= t
2
÷
t
1
(-1, -2, -3, -4, -1H, -5H)
45.0
50.0
55.0
%
-
-
-
-
-
-
2.20
1.50
1.50
ns
ns
ns
Rise Time
[7]
(-1, -2, -3, -4)
t
3
Rise Time
[7]
(-1H, -5H)
-
-
-
-
-
-
2.20
1.50
1.25
ns
ns
ns
Fall Time
[7]
(-1, -2, -3, -4)
t
4
Fall Time
[7]
(-1H, -5H)
5
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